Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.8.4. 10G Datapath Configurations with Native PHY IP

Table 43.  10G PCS Datapath ConfigurationsThe table lists the 10G PCS datapath configuration for 10/40/100 Gigabit Ethernet, 10/40/100 Gigabit Ethernet with 1588, Interlaken, 10G SDI, and other 10G protocols.
Transceiver PHY IP Native PHY IP
Link 10/40/100GBASE-R/KR 10/40/100GBASE-R with 1588 Interlaken SFI-5.2 10G SDI Other 10G Protocols (Basic Mode)
Lane Datarate 10.3125Gbps 10.3125Gbps 3.125 - 14.1 Gbps 0.6 - 14.1 Gbps 14 10.692Gbps 0.6 - 14.1 Gbps 14
PMA Channel Bonding Option15 16 Non-bonded, xN,feedback compensation Non-bonded, xN, feedback compensation Non-bonded Non-bonded, xN, feedback compensation Non-bonded, xN, feedback compensation Non-bonded, xN, feedback compensation
PCS Datapath 10G PCS 10G PCS 10G PCS 10G PCS 10G PCS 10G PCS
PCS-PMA Interface Width (Serialization Factor) 40-bit 40-bit 40-bit 32/40/64-bit 40-bit 32/40/64-bit
Gearbox Ratios 66:40 17 66:40 17 67:40 32:32, 64:3217, 40:40, 64:64 50:40 17 32:32, 64:3217, 40:40, 66:4017, 64:64
Block Synchronizer Enabled Enabled Enabled Bypassed (Low Latency Mode) Bypassed (Low Latency Mode) Bypassed (Low Latency Mode)
Disparity Generator, Checker Bypassed Bypassed Enabled Bypassed (Low Latency Mode) Bypassed (Low Latency Mode) Bypassed (Low Latency Mode)
Scrambler, Descrambler Enabled Enabled Enabled Bypassed (Low Latency Mode) Bypassed (Low Latency Mode) Bypassed (Low Latency Mode)
64B/66B Encoder, Decoder Enabled Enabled Bypassed Bypassed (Low Latency Mode) Bypassed (Low Latency Mode) Bypassed (Low Latency Mode)
BER Monitor Enabled Enabled Bypassed Bypassed (Low Latency Mode) Bypassed (Low Latency Mode) Bypassed (Low Latency Mode)
CRC32 Generator, Checker Bypassed Bypassed Enabled Bypassed (Low Latency Mode) Bypassed (Low Latency Mode) Bypassed (Low Latency Mode)
Frame Generator, Synchronizer Bypassed Bypassed Enabled Bypassed (Low Latency Mode) Bypassed (Low Latency Mode) Bypassed (Low Latency Mode)
RX FIFO (Mode) Clock Compensation Mode Registered Mode Interlaken Mode Phase Compensation Mode Phase Compensation Mode Phase Compensation Mode (Low Latency Mode)
TX FIFO (Mode) Phase Compensation Mode Registered Mode Interlaken Mode Phase Compensation Mode Phase Compensation Mode Phase Compensation Mode (Low Latency Mode)
TX/RX 10G PCS Latency (Parallel Clock Cycles) 18

TX: 8-12

RX: 15-34

TX: 1-4

RX: 2-5

TX: 7-28

RX: 14-21

TX: 6-10 (64:32)

TX: 7-10 (64:64, 40:40, 32:32)

RX: 6-10 (64:32)

RX: 7-10 (64:64, 40:40, 32:32)

TX: 7-11

RX: 6-12

TX: 6-10 (64:32)

TX: 6-11 (66:40)

TX: 7-10 (64:64, 40:40, 32:32)

RX: 6-10 (64:32)

RX: 6-11 (66:40)

RX: 7-10 (64:64, 40:40, 32:32)

FPGA Fabric-to- Transceiver Interface Widths 66-bit 66-bit 67-bit

32-bit

40-bit

64-bit

50-bit

32-bit

40-bit

64-bit

66-bit

FPGA Fabric-to- Transceiver Interface Width Maximum Frequencies 66-bit: 156.25 MHz 66-bit: 156.25 MHz 67-bit: 78.125-312.5 MHz 19

32-bit (32:32): 340.0 MHz

40-bit (40:40): 312.5 MHz

64-bit (64:32): 170.0 MHz

20

64-bit (64:64): 195.4 MHz

50-bit: 213.8 MHz 19

32-bit (32:32): 340.0 MHz

40-bit (40:40): 312.5 MHz

64-bit (64:32): 170.0 MHz

20

64-bit (64:64): 195.4 MHz

66-bit (66:40): 189.4 MHz

19
14 Gearbox ratios of 64:32 and 32:32 have a maximum supported datarate of 13.6 Gbps.
15 For xN bonding, the number of bonded channels is up to four using CMU PLL and up to six using ATX PLL, provided the data rate is supported by the CMU PLL and ATX PLL.
16 Bonding more than six channels requires PLL feedback compensation bonding. PLL feedback compensation bonding requires one PLL per transceiver bank and the PLL reference clock frequency must have the same value as the lane data rate divided by the serialization factor.
17 May require the use of an internal fractional PLL (fPLL) for selected Gearbox ratio.
18 PCS Latency values are with default recommended FIFO partially full and partially empty values. Disabled if Standard PCS 8B/10 Encoder/Decoder is used.
19 PCS tx_clkout frequency output is lane datarate/40 for 10G-SDI, Interlaken, and Basic Mode.
20 PCS tx_clkout frequency output is lane datarate/32 for SFI-S and Basic Mode.

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