Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

1.3.1.1. Word Aligner

Because the data is serialized before transmission and then deserialized at the receiver, the data loses the word boundary of the upstream transmitter after deserialization. The word aligner receives parallel data from the deserializer and restores the word boundary based on a pre-defined alignment pattern that must be received during link synchronization.

Serial protocols such as PCIe specify a standard word alignment pattern. For proprietary protocols, the transceiver architecture allows you to select a custom word alignment pattern specific to your implementation.

In addition to restoring the word boundary, the word aligner also implements the following features:

  • Synchronization state machine in configurations such as PCIe
  • Programmable run length violation detection in all configurations
  • Receiver polarity inversion in all configurations except PCIe
  • Receiver bit reversal in custom configurations
  • Receiver byte reversal in custom 16- and 20-bit width configurations

Depending on the configuration, the word aligner operates in one of the following modes:

  • Manual alignment
  • Automatic synchronization state machine
  • Bit-slip
  • Deterministic latency state machine
Table 6.  Word Aligner Options
Configuration PMA-PCS Interface Width (Bits) Word Alignment Mode Word Alignment Pattern Length Word Alignment Behavior
Custom 8- and 10-Bit Width 8 Manual Alignment 16 bits User-controlled signal starts the alignment process. Alignment happens once unless the signal is reasserted.
Bit-Slip N/A User-controlled signal shifts data one bit at a time.
10 Manual Alignment 7 and 10 bits User-controlled signal starts the alignment process. Alignment happens once unless the signal is reasserted.
Bit-Slip N/A User-controlled signal shifts data one bit at a time.
Automatic Synchronized State Machine 7 and 10 bits Data is required to be 8B/10B encoded. Aligns to the selected word aligner pattern.
Deterministic Latency State Machine 10 bits Data is required to be 8B/10B encoded. Aligns to the selected word aligner pattern.
Custom 16- and 20-Bit Width 16 Manual Alignment 8, 16, and 32 bits User-controlled signal starts the alignment process. Alignment happens once unless the signal is reasserted.
Bit-Slip N/A User-controlled signal shifts data one bit at a time.
20 Manual Alignment 7, 10, and 20 bits User-controlled signal starts the alignment process. Alignment happens once unless the signal is reasserted.
Bit-Slip N/A User-controlled signal shifts data one bit at a time.
Automatic Synchronized State Machine 7, 10, and 20 bits Data is required to be 8B/10B encoded. Aligns to the selected word aligner pattern.
Deterministic Latency State Machine 10 and 20 bits Data is required to be 8B/10B encoded. Aligns to the selected word aligner pattern.
PCIe 10 Automatic Synchronized State Machine 10 bits Automatically selected word aligner pattern length and pattern.

Example of Manual Alignment Mode Word Aligner with a 10-Bit PMA-PCS Interface Configuration

In basic single-width mode with a 10-bit PMA-PCS interface, you can configure the word aligner in manual alignment mode by selecting the Use manual word alignment mode option in the IP Catalog.

In manual alignment mode, the word alignment operation is manually controlled with the rx_std_wa_patternalign input signal or the rx_enapatternalign register. The word aligner operation is level-sensitive to rx_enapatternalign. If rx_enapatternalign is held high, the word aligner looks for the programmed 7-bit or 10-bit word alignment pattern in the received data stream. It updates the word boundary if it finds the word alignment pattern in a new word boundary. If rx_enapatternalign is de-asserted low, the word aligner maintains the current word boundary even when it sees the word alignment pattern in a new word boundary.

Two status signals, rx_syncstatus and rx_patterndetect, with the same latency as the datapath, are forwarded to the FPGA fabric to indicate the word aligner status. After receiving the first word alignment pattern after the rx_enapatternalign signal is asserted high, both therx_syncstatus and rx_patterndetect signals are driven high for one parallel clock cycle. Any word alignment pattern received thereafter in the same word boundary causes only the rx_patterndetect signal to go high for one clock cycle. Any word alignment pattern received thereafter in a different word boundary causes the word aligner to re-align to the new word boundary only if the rx_enapatternalign signal is held high. The word aligner asserts the rx_syncstatus signal for one parallel clock cycle whenever it re-aligns to the new word boundary.

In this example, a /K28.5/ (10'b0101111100) is specified as the word alignment pattern. The word aligner aligns to the /K28.5/ alignment pattern in cycle n because the rx_enapatternalign signal is asserted high. The rx_syncstatus signal goes high for one clock cycle, indicating alignment to a new word boundary. The rx_patterndetect signal also goes high for one clock cycle to indicate initial word alignment. At time n + 1, the rx_enapatternalign signal is de-asserted to instruct the word aligner to lock the current word boundary. The alignment pattern is detected again in a new word boundary across cycles n + 2 and n + 3. The word aligner does not align to this new word boundary because the rx_enapatternalign signal is held low. The /K28.5/ word alignment pattern is detected again in the current word boundary during cycle n + 5, causing the rx_patterndetect signal to go high for one parallel clock cycle.

Figure 20. Word Aligner with 10-Bit PMA-PCS Manual Alignment Mode


Note: If the word alignment pattern is known to be unique and does not appear between word boundaries, you can constantly hold rx_enapatternalign high because there is no possibility of false word alignment. If there is a possibility of the word alignment pattern occurring across word boundaries, you must control rx_enapatternalign to lock the word boundary after the desired word alignment is achieved to avoid re-alignment to an incorrect word boundary.

Example of Bit-Slip Mode Word Aligner with an 8-Bit PMA-PCS Interface Configuration

In a custom width configuration with an 8-bit PMA-PCS interface width, you can configure the word aligner in bit-slip mode. In bit-slip mode, the word aligner operation is controlled by the rx_bitslip bit of the pcs8g_rx_wa_control register. At every 0-1 transition of the rx_bitslip bit of the pcs8g_rx_control register, the bit-slip circuitry slips one bit into the received data stream, effectively shifting the word boundary by one bit. Also in bit-slip mode, the word aligner pcs8g_rx_wa_status register bit for rx_patterndetect is driven high for one parallel clock cycle when the received data after bit-slipping matches the 16-bit word alignment pattern programmed.

You can implement a bit-slip controller in the FPGA fabric that monitors the rx_parallel_data signal, the rx_patterndetect signal, or both, and controls the rx_bitslip signal to achieve word alignment.

For this example, consider that 8'b11110000 is received back-to-back and 16'b0000111100011110 is specified as the word alignment pattern. A rising edge on the rx_bitslip signal at time n + 1 slips a single bit 0 at the MSB position, forcing the rx_dataout to 8'b01111000. Another rising edge on the rx_bitslip signal at time n + 5 forces rx_dataout to 8'b00111100. Another rising edge on the rx_bitslip signal at time n + 9 forces rx_dataout to 8'b00011110. Another rising edge on the rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. At this instance, rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111, respectively, which matches the specified 16-bit alignment pattern 16'b0000111100011110. This results in the assertion of the rx_patterndetect signal.

Figure 21. Word Aligner Configured in Bit-Slip Mode


Example of Automatic Synchronization State Machine Mode Word Aligner with a 10-Bit PMA-PCS Interface Configuration

Protocols such as PCIe require the receiver PCS logic to implement a synchronization state machine to provide hysteresis during link synchronization. Each of these protocols defines a specific number of synchronization code groups that the link must receive to acquire synchronization, and a specific number of erroneous code groups that the protocol must receive to fall out of synchronization.

In PCIe configurations, the word aligner is in automatic synchronization state machine mode. The word aligner automatically selects the word alignment pattern length and pattern as specified by each protocol.

The synchronization state machine parameters are fixed for PCIe configurations as specified by the respective protocol.

Table 7.  Synchronization State Machine Modes for a PCI-Express (PIPE) Configuration 
Mode PCIe
Number of valid synchronization code groups or ordered sets received to achieve synchronization 4
Number of erroneous code groups received to lose synchronization 17
Number of continuous good code groups received to reduce the error count by one 16

After deassertion of the rx_digitalreset signal in automatic synchronization state machine mode, the word aligner starts looking for the word alignment pattern or synchronization code groups in the received data stream. When the programmed number of valid synchronization code groups or ordered sets is received, the rx_syncstatus status bit is driven high to indicate that synchronization is acquired. The rx_syncstatus status bit is constantly driven high until the programmed number of erroneous code groups is received without receiving intermediate good groups, after which rx_syncstatus is driven low. The word aligner indicates loss of synchronization (rx_syncstatus remains low) until the programmed number of valid synchronization code groups are received again.

Word Aligner in Deterministic Latency State Machine Mode

In deterministic latency state machine mode, word alignment is achieved by performing a clock-slip in the deserializer until the deserialized data coming into the receiver PCS is word-aligned.

The state machine controls the clock-slip process in the deserializer after the word aligner has found the alignment pattern and identified the word boundary. Deterministic latency state machine mode offers a reduced latency uncertainty in the word alignment operation for applications that require deterministic latency.

After rx_syncstatus is asserted and if the incoming data is corrupted causing an invalid code group, rx_syncstatus remains asserted. The rx_errdetect register will be set to 1 (indicating RX 8B/10B error detected). When this happens, the manual alignment mode is not be able to de-assert the rx_syncstatus signal. You must manually assert rx_digitalreset or manually control rx_std_wa_patternalign to resynchronize a new word boundary search whenever rx_errdetect shows an error.

Table 8.  Word Alignment in Deterministic Latency State Machine Mode
PCS Mode PMA-PCS Interface Width Word Alignment Operation
Single Width 10 bits
  1. After rx_digitalreset deasserts, the word aligner starts looking for the predefined word alignment pattern, or its complement, in the received data stream and automatically aligns to the new word boundary.
  2. After the pattern is found and the word boundary is identified, the state machine controls the clock-slip process in the deserializer.
  3. When the clock-slip is complete, the deserialized data coming into the receiver PCS is word-aligned and is indicated by the value 1 in the rx_syncstatus register until rx_digitalreset is asserted.
  4. To resynchronize to the new word boundary, the Avalon-MM register rx_enapatternalign (not available as a signal) must be reasserted to initiate another pattern alignment. Asserting rx_enapatternalign may cause the extra shifting in the RX datapath if rx_enablepatternalign is asserted while bit slipping is in progress. Consequently, rx_enapatternalign should only be asserted under the following conditions:
    • rx_syncstatus is asserted
    • rx_bitslipboundaryselectout changes from a non-zero value to zero or 1
  5. When the word aligner synchronizes to the new word boundary, rx_syncstatus has a value of 1 until rx_digitalreset is deasserted or rx_enapatternalign is set to 1. rx_patterndetect has a value of 1 whenever a word alignment pattern is found for one parallel clock cycle regardless of whether or not the word aligner is triggered to align to the new word boundary.
Double Width 20 bits

Programmable Run Length Violation Detection

The programmable run length violation circuit resides in the word aligner block and detects consecutive 1s or 0s in the data. If the data stream exceeds the preset maximum number of consecutive 1s or 0s, the violation is signified by the assertion of the rx_rlv status bit.

Table 9.  Detection Capabilities of the Run Length Violation Circuit
PMA-PCS Interface Width (Bits) Run Length Violation Detector Range
Minimum Maximum
8 4 128
10 5 160
16 8 512
20 10 640

Receiver Polarity Inversion

The positive and negative signals of a serial differential link may be erroneously swapped during board layout. Solutions such as board re-spin or major updates to the PLD logic are expensive. The receiver polarity inversion feature is provided to correct this situation.

Receiver Bit Reversal

By default, the receiver assumes an LSB-to-MSB transmission. If the transmission order is MSB-to-LSB, the receiver forwards the bit-flipped version of the parallel data to the FPGA fabric on rx_parallel_data. For example, if in 8 bit width mode, D[7:0] is rewired to D[0:7].

Receiver Byte Reversal in Custom 16- and 20-Bit Width Configurations

The MSByte and LSByte of the input data to the transmitter may be erroneously swapped. The receiver byte reversal feature corrects this situation.

Figure 22. Receiver Byte Reversal Feature

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