Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

3.6. Document Revision History

Date Version Changes
January 2016 2016.01.11 Added third note to the "User-Coded Reset Controller" section.
September 2014 2014.09.30
  • Added statement at the top of the chapter that an embedded reset controller is provided, but you can provide your own reset controller instead.
  • Added information about deasserting signals to the "Resetting the Transceiver with the PHY IP Embedded Reset Controller during Device Power-Up" section.
  • Added "Control Signals" and "Status Signals" labels to the timing diagrams.
  • Added a link to the Related Links in the "Clock Data Recovery in Manual Lock Mode" section.
October 2013 2013.10.11
  • Changed term of User-Controlled Reset Controller to User-Coded Reset Controller.
May 2013 2013.05.06
  • Added information about ATX PLL calibration.
  • Changes to figures to reflect correct values for tpll_lock.
  • Added link to the known document issues in the Knowledge Base.
February 2013 2013.02.21
  • Added information about reset options.
  • Clarified content about resetting the transmitter with the user-controlled reset controller during power-up.
  • Updated incorrect description of pll_powerdown when using Memory Map registers.
December 2012 2012.12.17
  • Added information about resetting the transceiver during power-up and device operation
  • Restructured document
June 2012 3.3
  • Updated for the Quartus II software version 12.0.
  • Revised Figure 3-2 , Figure 3-4 , and Figure 3-6 .
  • Added new Table 3-1.
  • Added new steps describing wave forms.
  • Deleted power-up Figures 3-2 and 3-5 and changed text accordingly.

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