Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

3.2.1. User-Coded Reset Controller Signals

Use the signals in the following figure and table with a user-coded reset controller.
Figure 80. Interaction Between the Transceiver PHY Instance, Transceiver Reconfiguration Controller, and the User-Coded Reset Controller


Table 25.  Signals Used by the Transceiver PHY instance, Transceiver Reconfiguration Controller, and User-Coded Reset Controller
Signal Name Signal Type Description
mgmt_clk_clk Clock Clock for the Transceiver Reconfiguration Controller. This clock must be stable before releasing mgmt_rst_reset.
mgmt_rst_reset Reset Reset for the Transceiver Reconfiguration Controller
pll_powerdown Control Resets the TX PLL when asserted high
tx_analogreset Control Resets the TX PMA when asserted high
tx_digitalreset Control Resets the TX PCS when asserted high
rx_analogreset Control Resets the RX PMA when asserted high
rx_digitalreset Control Resets the RX PCS when asserted high
reconfig_busy Status A high on this signal indicates that reconfiguration is active
tx_cal_busy Status A high on this signal indicates that TX calibration is active
rx_cal_busy Status A high on this signal indicates that RX calibration is active
pll_locked Status A high on this signal indicates that the TX PLL is locked
rx_is_lockedtoref Status A high on this signal indicates that the RX CDR is in the lock to reference (LTR) mode
rx_is_lockedtodata Status A high on this signal indicates that the RX CDR is in the lock to data (LTD) mode

Did you find the information on this page useful?

Characters remaining:

Feedback Message