Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

1.5. PCIe Gen3 PCS Architecture

Stratix V architecture supports the PCIe Gen3 specification. The PCIe Gen3 uses a 128/130 bit block encoding/decoding scheme which is different from the 8B/10B scheme used in Gen1 and Gen2. The 130-bit block contains a 2-bit sync header and 128-bit data payload. For this reason, Stratix V devices include a separate Gen3 PCS that supports functionality at Gen3 speeds. You can use Altera hard IP and interface to the transceivers, or you can implement your MAC and connect it to the transceiver through the PIPE interface.

This PIPE interface supports the seamless switching of Data and Clock between the Gen1, Gen2, and Gen3 PCS, and provides support for PIPE 3.0 features.

Figure 40. PCIe Gen3 PCS Top Level Block DiagramThe RX/TX Phase Comp FIFOs are physically placed in, and shared with, the Standard PCS.

Did you find the information on this page useful?

Characters remaining:

Feedback Message