Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
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Document Table of Contents

2.2.1.1. Transmitter Clock Lines

The transmitter clock network consists of two types of dedicated clocking resources.

The dedicated clocking resources are:

  • Non-bonded configurations
  • x1 clock lines
  • xN clock lines (in non-bonded configurations available only for Native PHY)
  • Bonded configurations (not available for GT transceiver channels)
  • x6 clock lines
  • x6 PLL Feedback Compensation
  • xN clock lines (available only for PCIe and Native PHY)
Note: The Quartus II software performs the clock routing related to the transmitter clock network based on the transceiver configuration selected.

Table 17.  Data Rates and Spans Supported Using Stratix V Clock Sources and Clock Networks
Clock Network Transceiver Channel Clock Source Max Data Rate Bonding Span
x1 GX ATX PLLs in a transceiver bank 14.1 Gbps4 No Transceiver bank
CMU PLLs in a transceiver bank 12.5 Gbps 4 Transceiver bank
Fractional PLLs in a transceiver bank 3.125 Gbps fPLLs can only span upper or lower 3 channels in a transceiver bank.
xN (Native PHY) GX ATX PLLs in a transceiver bank provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The xN clock lines receive only the serial clock from the x6 clock lines. 8 Gbps No xN lines span a side of the device. Specified datarate can drive up to 13 data channels above and up to 13 data channels below TX PLL.
Channel PLLs in a transceiver bank provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The xN clock lines receive only the serial clock from the x6 clock lines. 7.99 Gbps
Fractional PLLs in a transceiver bank provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The xN clock lines receive only the serial clock from the x6 clock lines. 3.125 Gbps
x1 GT Bottom ATX PLL in a GT transceiver bank 28 Gbps 4 No Transceiver bank
x6 GX ATX PLLs in a transceiver bank provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The x6 clock lines receive both the serial and parallel clock from the central clock dividers. 14.1 Gbps 4 Yes Transceiver bank
The channel (CMU) PLLs provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The x6 clock lines receive both the serial and parallel clock from the central clock dividers. 12.5 Gbps 4
Fractional PLLs provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The x6 clock lines receive both the serial and parallel clock from the central clock dividers. 3.125 Gbps
x6 PLL Feedback Compensation 5 One ATX PLL per bonded transceiver bank provides a serial clock to the central clock dividers of Ch 1 and Ch 4. The central clock dividers in the transceiver bank drive the x6 clock lines and provide feedback path to the ATX PLL. The x6 clock lines receive both the serial and parallel clocks from the central clock dividers. 14.1 Gbps 4 Yes x6 lines span a transceiver bank. The x6 lines across multiple transceiver banks can be bonded together through PLL feedback compensation path to span the entire side of the device.
One CMU PLL per bonded transceiver bank provides a serial clock to the central clock dividers of Ch 1 and Ch 4. The central clock dividers in the transceiver bank drive the x6 clock lines and provide feedback path to the CMU PLL. The x6 clock lines receive both the serial and parallel clocks from the central clock dividers. 12.5 Gbps 4
xN (PCIe)6 GX The ATX or channel (CMU) PLL provides a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The xN clock lines receive the serial and parallel clocks from the x6 clock lines. 8 Gbps Yes xN lines span a side of the device, but can bond only up to eight contiguous data channels.
xN (Native PHY) GX ATX PLLs in a transceiver bank provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The xN clock lines receive the serial and parallel clocks from the x6 clock lines. 9.8304 Gbps 4 Yes xN lines span a side of the device. Specified datarate can bond up to 7 contiguous data channels above and up to 7 contiguous data channels below TX PLL.
8 Gbps Yes xN lines span a side of the device. Specified datarate can bond up to 13 contiguous data channels above and up to 13 contiguous data channels below TX PL
Channel (CMU) PLLs in a transceiver bank provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The xN clock lines receive the serial and parallel clocks from the x6 clock lines. 7.99 Gbps Yes xN lines span a side of the device. Specified datarate can bond up to 13 contiguous data channels above and up to 13 contiguous data channels below TX PL
Fractional PLLs (fPLLs) in a transceiver bank provide a serial clock to the central clock dividers of Ch1 and Ch4. The central clock dividers in the transceiver bank drive the x6 clock lines. The xN clock lines receive the serial and parallel clocks from the x6 clock lines. 3.125 Gbps
Note: Stratix V devices 5SGXB5, 5SGXB6, 5SGSB, and 5SGSB have one transceiver bank on each side with only three transceiver channels. For more information, refer to the Transceiver Architecture in Stratix V Devices chapter.
Figure 51. x1 Clock Lines Used by GX Transmitter Channels for Non-Bonded Configuration


The x1 clock lines route the serial clock to the clock dividers of any channel within a transceiver bank. Refer to Table 17 for details. The channel PLL, if configured as a CMU PLL, can drive the clock divider of its own channel, but you will not be able to use the channel PLL as a CDR. Without a CDR, you can use the channel only as a transmitter channel.

The x6 clock lines are used for bonded configurations within transceiver banks and PLL Feedback Compensation when bonding across multiple transceiver banks. The x6 clock lines are also used to route both the serial clock and parallel clock from the central clock dividers to the transceiver channels. When spanning across multiple transceiver banks, the xN clock lines can be used for both non-bonded configuration and bonded configurations.

The central clock dividers of channel 1 and channel 4 in a transceiver bank drive the x6 clock lines. The x6 clock lines then drive the xN clock lines. The xN clock lines used for both non-bonded and bonded configurations, span the entire side of the device and can provide the serial and parallel clock to contiguous channels within or outside a transceiver bank.

For both xN bonded and xN non-bonded configurations, the xN clock lines can support up to 13 contiguous channels above and up to 13 contiguous channels below the selected transmitter PLL which drives the central clock dividers of channel 1 or channel 4 of the same transceiver bank.

Figure 52. Channel Span for xN Bonded and Non Bonded Configurations


For xN bonded configurations, the channel where the central clock divider resides (channel 1 or 4) can be used as a data channel. Hence, a total of up to 27 contiguous data channels can be supported in the bonded configuration with the xN clock lines. However, for xN non-bonded configurations, the channel 1 or channel 4 of the transceiver bank where the central clock divider resides cannot be used as a data channel since the parallel clock cannot be generated in this channel. Hence, a total of up to 26 contiguous data channels can be supported in the non-bonded configuration with the xN clock lines.

Figure 53. x6 and xN Clock Lines Used for Bonded Configurations


4 For the fastest speed grade only. For the remaining speed grades, refer to the Stratix V Device Datasheet.
5 The input reference clock frequency of the transmit PLL must be the same as the parallel clock frequency which clock the PCS bonded channels.
6 For more information about PCIe x8 configurations, refer to the section titled “Hard IP x8 Configuration” in the Transceiver Configurations in Stratix V Devices chapter.

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