Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.3.2. Receiver Datapath Interface Clock

The receiver datapath interface consists of the following:
  • Read side of the RX phase compensation FIFO—for configurations that use the standard PCS channel
  • Read side of the RX FIFO—for configurations that use the 10G PCS channel

This interface is clocked by the receiver datapath interface clock. The receiver PCS forwards the following clocks to the FPGA fabric:

  • rx_clkout—for each receiver channel in a non-bonded configuration when you do not use a rate matcher
  • tx_clkout—for each receiver channel in a non-bonded configuration when you use a rate matcher
  • single rx_clkout[0]—for all receiver channels in a bonded configuration
Figure 73. Receiver Datapath Interface Clocking


All configurations that use the standard PCS channel must have a 0 ppm difference between the receiver datapath interface clock and the read side clock of the RX phase compensation FIFO.

Note: For more information about interface clocking for each configuration, refer to the clocking sections for each configuration in the Transceiver Configurations in Stratix V Devices chapter.

You can clock the receiver datapath interface by using one of the following:

  • Quartus II-selected receiver datapath interface clock
  • User-selected receiver datapath interface clock
Note: User-selection is provided to share the transceiver datapath interface clocks to reduce GCLK, RCLK, and PCLK resource utilization in your design.

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