Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

3.1.3. Resetting the Transceiver with the PHY IP Embedded Reset Controller During Device Operation

Follow this reset sequence to reset the entire transceiver at any point during the device operation, to re-establishing a link, or after certain dynamic reconfigurations.

The numbers in the following figure correspond to the numbered list, which guides you through the transceiver reset sequence during device operation.

  1. Assert phy_mgmt_clk_reset for two phy_mgmt_clk clock cycles to re-start the entire transceiver reset sequence.
  2. After the transmitter reset sequence is complete, the tx_ready status signal is asserted and remains asserted to indicate that the transmitter is ready to transmit data.
  3. After the receiver reset sequence is complete, the rx_ready status signal is asserted and remains asserted to indicate that the receiver is ready to receive data.
Note: If the tx_ready and rx_ready signals do not stay asserted, the reset sequence did not complete successfully and the link will be down.
Figure 79. Reset Sequence Timing Diagram Using Embedded Reset Controller during Device Operation


Note: To reset the transmitter and receiver analog and digital blocks separately without repeating the entire reset sequence, use the Avalon Memory Map registers.

Did you find the information on this page useful?

Characters remaining:

Feedback Message