Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

3. Transceiver Reset Control in Stratix V Devices

Altera’s recommended reset sequence ensures that both the physical coding sublayer (PCS) and physical medium attachment (PMA) in each transceiver channel are initialized and functioning correctly.

The Stratix V transceiver reset sequence is mandatory to initialize the physical coding sublayer (PCS) and physical medium attachment (PMA) blocks. Multiple reset options are available to reset the analog and digital portions of the transmitter and receiver.

Altera provides an embedded reset controller, but you can also provide your own user-coded reset controller.

Table 23.  Stratix V Reset Control Options
Transceiver PHY IP Core Embedded Reset Controller User-Coded Reset Controller Transceiver PHY Reset Controller IP Avalon Memory-Mapped Reset Registers
XAUI Yes Yes
PCI Express Yes Yes
10GBASE-R Yes Yes Yes Yes
Interlaken Yes Yes
Custom Configuration Yes Yes Yes Yes
Low Latency Yes Yes Yes Yes
Deterministic Latency Yes Yes Yes Yes
Native PHY Yes Yes

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