Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
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2.2.2.3. Transmitter GT Channel Clocking

In a Stratix V GT transmitter channel the central clock divider block provides the serial and the parallel clocks to the serializer.
Figure 63. GT Channel Transmitter Clocking


In a Stratix V GT transmitter channel, the parallel clock is forwarded to the FPGA fabric to provide an interface between the FPGA fabric and the transceiver. All PCS functions, such as encoding and bit slipping, must be implemented in the FPGA core.

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