Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
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3.3.1. Transceiver Reset Control Signals Using Avalon Memory Map Registers

The following table lists the memory map registers for CDR lock mode and channel reset. These signals help you reset your transceiver when you use Memory Map registers within the PHY IP.
Table 27.  Transceiver Reset Control Using Memory Map Registers
Register Name Description
pma_rx_set_locktodata

This register is for CDR manual lock mode only. When you set the register to high, the RX CDR PLL is in the lock to data (LTD) mode. The default is low when both registers have the CDR in auto lock mode.

pma_rx_set_locktoref

This register is for CDR manual lock mode only. When you set the register to high, the RX CDR PLL is in the lock to reference (LTR) mode if pma_rx_set_lockedtodata is not asserted. The default is low when both registers have the CDR in auto lock mode.

reset_tx_digital

When you set this register to high, the tx_digitalreset signal is asserted in every channel that is enabled for reset control through the reset_ch_bitmask register. To deassert the tx_digitalreset signal, set the reset_tx_digital register to 0.

reset_rx_analog

When you set this register to high, the rx_analogreset signal is asserted in every channel that is enabled for reset control through the reset_ch_bitmask register. To deassert the rx_analogreset signal, set the reset_rx_analog register to 0.

reset_rx_digital

When you set this register to high, the rx_digitalreset signal is asserted in every channel that is enabled for reset control through the reset_ch_bitmask register. To deassert the rx_digitalreset signal, set the reset_rx_digital register to 0.

reset_ch_bitmask The registers provide an option to enable or disable certain channels in a PHY IP instance for reset control. By default, all channels in a PHY IP instance are enabled for reset control.
pll_powerdown

When asserted, the TX phase-locked loop (PLL) is turned off.

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