Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
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4.6.5. CPRI Enhancements

The deterministic latency state machine in the word aligner reduces the known delay variation from the word alignment process and automatically synchronizes and aligns the word boundary by slipping a clock cycle in the deserializer. Incoming data to the word aligner is aligned to the boundary of the word alignment pattern (K28.5). User logic is not required to manipulate the TX bit slipper for constant round-trip delay. In manual mode, the TX bit slipper is able to compensate one unit interval (UI).

The word alignment pattern (K28.5) position varies in byte deserialized data. Delay variation is up to ½ parallel clock cycle. You must add in extra user logic to manually check the K28.5 position in byte deserialized data for the actual latency.

Figure 137. Deterministic Latency State Machine in the Word Aligner


Table 40.  Methods to Achieve Deterministic Latency Mode in Stratix V Devices
Existing Feature Enhanced Feature
Description Requirement Description Requirement
Manual alignment with bit position indicator provides deterministic latency. Delay variation up to 1 parallel clock cycle Extra user logic to manipulate the TX bit slipper with a bit position indicator from the word aligner for constant total round-trip delay Deterministic latency state machine alignment reduces the known delay variation in word alignment operation None

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