Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.1. Protocols and Transceiver PHY IP Support

Table 30.  Protocols and PHY IP Features Support
Protocol Standard Transceiver IP PCS Type Avalon-MM Register Interface Reset Controller
PCIe Gen3 x1, x2, x4, x8 PHY IP Core for PCIe (PIPE) 10 Standard and Gen3 Yes Embedded
PCIe Gen2 x1, x2, x4, x8 PHY IP Core for PCIe (PIPE) 10 Standard Yes Embedded
PCIe Gen1 x1, x2, x4, x8 PHY IP Core for PCIe (PIPE) 10 Standard Yes Embedded
10GBASE-R 10GBASE-R 10G Yes Embedded
Native PHY 10G No External Reset IP
10G/40/100G Ethernet Native PHY 10G No External Reset IP
1G/10Gb Ethernet 1G/10GbE and 10GBASE-KR Standard and 10G Yes Embedded
1G/10Gb Ethernet with 1588 1G/10GbE and 10GBASE-KR Standard and 10G Yes Embedded
10G Ethernet with 1588 Native PHY 10G No External Reset IP
10GBASE-KR and 1000BASE-X 1G/10GbE and 10GBASE-KR Standard and 10G Yes Embedded
1000BASE-X and SGMII Gigabit Ethernet Custom PHY Standard Standard Yes Embedded or External Reset IP
XAUI XAUI PHY IP Standard Soft-PCS Yes Embedded
SPAUI Low Latency PHY Standard and 10G Yes Embedded or External Reset IP
Native PHY Standard and 10G No External Reset IP
DDR XAUI Low Latency PHY Standard and 10G Yes Embedded or External Reset IP
Native PHY Standard and 10G No External Reset IP
Interlaken (CEI-6G/11G) Interlaken PHY 10G Yes Embedded
Native PHY 11 10G No External Reset IP
OTU-4 (100G) via OIF SFI-S Low Latency PHY 10G Yes External Reset IP
Native PHY 10G No External Reset IP
OTU-3 (40G) via OIF SFI-5.2/SFI-5.1 Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
OTU-2 (10G) via OIF SFI-5.1s Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
OTU-1 (2.7G) Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.2 Low Latency PHY 10G Yes Embedded or External Reset IP
Low Latency PHY Standard Yes Embedded or External Reset IP
SONET/SDH STS-768/STM-256 (40G) via OIF SFI-5.2/SFI-5.1 Native PHY Standard and 10G No External Reset IP
SONET/SDH STS-192/STM-64 (10G) via SFP+/SFF-8431/ CEI-11G Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
SONET/SDH STS-192/STM-64 (10G) via OIF SFI-5.1s/SxI-5/ SFI-4.2 Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET STS-96 (5G) via OIF SFI-5.1s Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET/SDH STS-48/STM-16 (2.5G) via SFP/TFI-5.1 Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SONET/SDH STS-12/STM-4 (0.622G) via SFP/TFI-5.1 Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
Intel QPI Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY PMA-Direct No External Reset IP
10G SDI Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
SD-SDI/HD-SDI/ 3G-SDI Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
10G GPON/EPON Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
GPON/EPON Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
16/10G Fibre Channel Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
8G/4G Fibre Channel Low Latency PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
FDR/FDR-10 Infiniband x1, x4, x12 Low Latency PHY 10G Yes Embedded or External Reset IP
Native PHY 10G No External Reset IP
SDR/DDR/QDR Infiniband x1, x4, x12 Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
CPRI 4.2/OBSAI RP3 v4.2 Deterministic PHY Standard Yes Embedded
Native PHY Standard No External Reset IP
SRIO 2.2/1.3 12 Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
SATA 3.0/2.0/1.0 and SAS 2.0/1.0 Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
HiGig+/2+ Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
JESD204A Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
ASI Custom PHY Standard Yes Embedded or External Reset IP
SPI 5 (50G) Custom PHY Standard Yes Embedded or External Reset IP
Native PHY Standard No External Reset IP
Custom and other protocols Native PHY Standard, 10G, and PMA-Direct No External Reset IP
10 Hard IP for PCI Express is also available as a Intel® FPGA IP core function.
11 A Soft-PCS bonding IP is required.
12 Nx Multi-Alignment Deskew State Machine must be implemented in the core.

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