Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Document Table of Contents

2.3. FPGA Fabric-Transceiver Interface Clocking

The FPGA fabric-transceiver interface clocks consist of clock signals from the FPGA fabric to the transceiver blocks and clock signals from the transceiver blocks to the FPGA fabric. These clock resources use the clock networks in the FPGA core, including the global (GCLK), regional (RCLK), and periphery (PCLK) clock networks.

The FPGA fabric-transceiver interface clocks can be subdivided into the following three categories:

  • Input reference clocks—Refer to Input Reference Clock Sources. The input reference clock can be an FPGA fabric-transceiver interface clock when it is also forwarded to the FPGA fabric to clock the logic in the FPGA fabric.
  • Transceiver datapath interface clocks—Used to transfer data, control, and status signals between the FPGA fabric and the transceiver channels. The transceiver channel forwards the tx_clkout signal to the FPGA fabric to clock the data and control signals into the transmitter. The transceiver channel also forwards the recovered rx_clkout clock (in configurations without the rate matcher) or the tx_clkout clock (in configurations with the rate matcher) to the FPGA fabric to clock the data and status signals from the receiver into the FPGA fabric.
  • Other transceiver clocks—Used to form a part of the FPGA fabric-transceiver interface clocks as follows:
  • phy_mgmt_clk—Avalon®-MM interface clock used for controlling the transceivers, dynamic reconfiguration, and calibration
  • fixed_clk—125 MHz fixed-rate clock used in the PCIe (PIPE) receiver detect circuitry
Table 19.  FPGA Fabric–Transceiver Interface Clocks
Clock Name Clock Description Interface Direction FPGA Fabric Clock Resource Utilization
pll_refclk, rx_cdr_refclk A transceiver PMA TX PLL and CDR reference clock, sourced by dedicated differential pins of the device. Input GCLK, RCLK, PCLK
tx_clkout, tx_pma_clkout Clock forwarded by the transceiver for clocking the transceiver datapath interface. The value of tx_clkout / tx_pma_clkout is derived by dividing the data rate by the serialization factor. For example, a 3 Gbps link with a serialization factor of 20 will result in a tx_clkout of 150 MHz. Transceiver-to-FPGA fabric
rx_clkout, rx_pma_clkout Clock forwarded by the receiver for clocking the receiver datapath interface. The value of rx_clkout / rx_pma_clkout is derived by dividing the data rate by the deserialization factor. For example, a 10 Gbps link with a deserialization factor of 40 will result in a rx_clkout of 250 MHz.
tx_10g_coreclkin/tx_std_coreclkin User-selected clock for clocking the transmitter datapath interface FPGA fabric-to-transceiver
rx_10g_coreclkin / rx_std_coreclkin User-selected clock for clocking the receiver datapath interface
fixed_clk PCIe receiver detect clock
phy_mgmt_clk 8 Avalon-MM interface management clock
Note: You can forward the pll_ref_clk, tx_clkout, and rx_clkout clocks to a fractional PLL so that the fractional PLL can synthesize a clock for the FPGA logic. A second fractional PLL can be reached by periphery clocks, depending on your device and channel placement, and may require using a RGCLK or GCLK.
Table 20.  Configuration Specific Port Names for tx_clkout and rx_clkout
Configuration Port Name for tx_clkout Port Name for rx_clkout
Custom tx_clkout rx_clkout
Native - 10G PCS tx_10g_clkout rx_10g_clkout
Native - Standard PCS tx_std_clkout rx_std_clkout
Native - PMA Direct tx_pma_clkout rx_pma_clkout
Interlaken tx_clkout rx_clkout
Low Latency tx_clkout rx_clkout
PCIe pipe_pclk pipe_pclk
XAUI xgmii_tx_clk xgmii_rx_clk
Note: For more information about the GCLK, RCLK, and PCLK resources available in each device, refer to the Clock Networks and PLLs in Stratix V Devices chapter.
8 The phy_mgmt_clk is a free-running clock that is not derived from the transceiver blocks, except if phy_mgmt_clk is derived from the dedicated refclk pin.

Did you find the information on this page useful?

Characters remaining:

Feedback Message