Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations

The CMU PLL or the auxiliary transmit (ATX) PLLs in a transceiver bank generate the transmitter serial and the fractional PLL for the parallel clocks for the 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX channels. The following table lists the configuration details.
Table 32.   Input Reference Clock Frequency and Interface Speed Specifications for 10GBASE-R, 10GBASE-KR, and 1000BASE-KX Configurations
PHY IP Type PHY Type Input Reference Clock Frequency (MHz) FPGA Fabric-Transceiver Interface Width FPGA Fabric-Transceiver Interface Frequency (MHz)
10GBASE-R PHY IP 10GBASE-R 644.53125, 322.265625 64-bit data, 8-bit control 156.25
1G/10GbE and 10GBASE-KR PHY IP 10GBASE-R and 10GBASE-KR 644.53125, 322.265625 64-bit data, 8-bit control 156.25
1G/10GbE and 10GBASE-KR PHY IP 1000BASE-X and 1000BASE-KX 125, 62.5 8-bit data, gmii_tx_en and gmii_tx_err control 125

Did you find the information on this page useful?

Characters remaining:

Feedback Message