188.8.131.52. Receiver Phase Compensation FIFO184.108.40.206. Receiver Phase Compensation FIFO
The receiver phase compensation FIFO is four words deep and interfaces the status and data signals between the receiver PCS and the FPGA fabric or the PCIe hard IP block. The FIFO supports the following operations:
- Phase compensation mode with various clocking modes on the read clock and write clock
- Registered mode with only one clock cycle of datapath latency
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