Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.8.2.1. Standard PCS Receiver and Transmitter Blocks

To implement a Native PHY link with the Standard PCS datapath, instantiate the Stratix V Transceiver Native PHY IP in the IP Catalog, under Transceiver PHY in the Interfaces menu. Select option to enable the Standard PCS by checking the box. A Standard PCS tab appears with the parameters and configuration options for each block.

The following blocks can be enabled or disabled and configured in the Standard PCS.

  • Word Aligner
  • Deskew FIFO
  • Rate Match FIFO
  • 8B/10B Encoder/Decoder
  • Byte Serializer/De-Serializer
  • Byte Ordering
  • Receive Phase Compensation FIFO (Can also be configured as registered mode)
  • Transmit Phase Compensation FIFO (Can also be configured as registered mode)
  • TX Bitslipper

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