Stratix V Device Handbook: Volume 2: Transceivers

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ID 683779
Date 11/23/2021
Public
Document Table of Contents

3.5. Transceiver Blocks Affected by the Reset and Powerdown Signals

The following table lists blocks that are affected by specific reset and powerdown signals.
Table 29.  Transceiver Blocks Affected
Transceiver Block pll_powerdown rx_digitalreset rx_analogreset tx_digitalreset tx_analogreset
PLL
CMU PLL Yes
ATX PLL Yes
Receiver Standard PCS
Receiver Word Aligner Yes
Receiver Deskew FIFO Yes
Receiver Rate Match FIFO Yes
Receiver 8B/10B Decoder Yes
Receiver Byte Deserializer Yes
Receiver Byte Ordering Yes
Receiver Phase Compensation FIFO Yes
Receiver 10G PCS
Receiver Gear Box Yes
Receiver Block Synchronizer Yes
Receiver Disparity Checker Yes
Receiver Descrambler Yes
Receiver Frame Sync Yes
Receiver 64B/66B Decoder Yes
Receiver CRC32 Checker Yes
Receiver FIFO Yes
Receiver PMA
Receiver Buffer Yes
Receiver CDR Yes
Receiver Deserializer Yes
Transmitter Standard PCS
Transmitter Phase Compensation FIFO Yes
Byte Serializer Yes
8B/10B Encoder Yes
Transmitter Bit-Slip Yes
Transmitter 10G PCS
Transmitter FIFO Yes
Transmitter Frame Generator Yes
Transmitter CRC32 Generator Yes
Transmitter 64B/66B Encoder Yes
Transmitter Scrambler Yes
Transmitter Disparity Generator Yes
Transmitter Gear Box Yes
Transmitter PMA
Transmitter Central/Local Clock Divider Yes
Serializer Yes
Transmitter Buffer Yes

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