Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2. Transceiver Clocking in Stratix V Devices

This chapter provides information about the Stratix® V transceiver clocking architecture. The chapter describes the clocks that are required for operation, internal clocking architecture, and clocking options when the transceiver interfaces with the FPGA fabric.

Notes:

  • Bonded configuration refers to PMA bonding for Arria V devices. The split between PCS and PMA bonding is done in Arria 10 devices only.
  • Channels need to be contiguous when using PMA bonding.
Figure 43. Transceiver Clocking Architecture Overview


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