2.2. Internal Clocking
|A||Transmitter Clock Network||Clock distribution from transmitter PLLs to channels|
|B||Transmitter Clocking||Clocking architecture within transmitter channel datapath|
|C||Receiver Clocking||Clocking architecture within receiver channel datapath|
The reference clock from one input source is fed to a transmitter PLL. The transmitter PLL could be either a channel PLL configured as a CMU PLL, or an ATX PLL, or a fractional PLL. The transmitter PLL generates a serial clock that is distributed using a transmitter clock network to the transceiver channels.
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