Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Document Table of Contents

2.2. Internal Clocking

In the internal clocking architecture, different physical coding sublayer (PCS) configurations and channel bonding options result in various transceiver clock paths.
Table 16.  Internal Clocking SubsectionsThe labels listed in the following table and shown in the figure following mark the three sections of the transceiver internal clocking.
Label Scope Description
A Transmitter Clock Network Clock distribution from transmitter PLLs to channels
B Transmitter Clocking Clocking architecture within transmitter channel datapath
C Receiver Clocking Clocking architecture within receiver channel datapath
Figure 49. Internal Clocking

The reference clock from one input source is fed to a transmitter PLL. The transmitter PLL could be either a channel PLL configured as a CMU PLL, or an ATX PLL, or a fractional PLL. The transmitter PLL generates a serial clock that is distributed using a transmitter clock network to the transceiver channels.

Note: The clocking described in this section is internal to the transceiver, and the clock routing is primarily performed by the Quartus® II software, based on the transceiver configuration selected.