Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.2.1. Transmitter Clock Network

The transmitter clock network routes the clock from the transmitter PLL to the transmitter channel.

The transmitter clock network provides two clocks to the transmitter channel:

  • Serial clock—high-speed clock for the serializer
  • Parallel clock—low-speed clock for the serializer and the PCS

Stratix V transceivers support various non-bonded and bonded transceiver clocking configurations. If you use a bonded configuration, both the serial clock and the PCS internal parallel clock are routed from the transmitter PLL to the transmitter channel. If you use a non-bonded configuration, then only the serial clock is routed from the transmitter PLL to the transmitter channel and the PCS internal parallel clock is generated by the clock divider of each channel.

Note: The reference clock and the PCS internal parallel clock are not the same. The reference clock as described in Input Reference Clocking is used to drive the transmit PLL, which generates the serial clock. The PCS internal parallel clock is derived from the serial clock, and equals the serial clock divided by the serialization factor of the serializer.
Figure 50. Transmitter Clock Network The following figure shows the transceiver clock network, beginning with the input reference clock, followed by the transmitter PLL, clock dividers, and ending with the x6 and xN clock lines.


Note: For more information about bonding, refer to the “Bonded Configurations” section of the Transceiver Architecture in Stratix V Devices chapter.

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