220.127.116.11.1. Non-Bonded Channel Configurations Using the x1 Clock Network 18.104.22.168.2. Non-Bonded Channel Configurations Using the xN Clock Network 22.214.171.124.3. Bonded Channel Configurations 126.96.36.199.4. Bonded Channel Configurations Using the xN Clock Network 188.8.131.52.5. Bonded Channel Configurations Using the PLL Feedback Compensation Path
3.2.1. User-Coded Reset Controller Signals 3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up 3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration 3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
4.1. Protocols and Transceiver PHY IP Support 4.2. 10GBASE-R and 10GBASE-KR 4.3. Interlaken 4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 4.5. XAUI 4.6. CPRI and OBSAI—Deterministic Latency Protocols 4.7. Transceiver Configurations 4.8. Native PHY IP Configuration 4.9. Stratix V GT Device Configurations 4.10. Document Revision History
4.2.1. 10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration 4.2.2. 10GBASE-R and 10GBASE-KR Supported Features 4.2.3. 1000BASE-X and 1000BASE-KX Transceiver Datapath 4.2.4. 1000BASE-X and 1000BASE-KX Supported Features 4.2.5. Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX Configurations 4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations
4.4.1. Transceiver Datapath Configuration 4.4.2. Supported Features for PCIe Configurations 4.4.3. Supported Features for PCIe Gen3 4.4.4. Transceiver Clocking and Channel Placement Guidelines 4.4.5. Advanced Channel Placement Guidelines for PIPE Configurations 4.4.6. Transceiver Clocking for PCIe Gen3
6.1. Dynamic Reconfiguration Features 6.2. Offset Cancellation 6.3. PMA Analog Controls Reconfiguration 6.4. On-Chip Signal Quality Monitoring (Eye Viewer) 6.5. Decision Feedback Equalization 6.6. Adaptive Equalization 6.7. Dynamic Reconfiguration of Loopback Modes 6.8. Transceiver PLL Reconfiguration 6.9. Transceiver Channel Reconfiguration 6.10. Transceiver Interface Reconfiguration 6.11. Document Revision History
184.108.40.206.4. Bonded Channel Configurations Using the xN Clock Network
Figure 61. Transmitter Channels in xN Bonded ConfigurationThe following figure shows 12 transmitter channels configured in a bonded configuration and driven by the ATX PLL of the transceiver bank 1. The ATX PLL drives the central clock divider of channel 1 in transceiver bank 1. The central clock divider of channel 1 generates a parallel clock and drives both the serial and parallel clocks on the x6 clock line. All bonded channels in transceiver bank 1 source both the serial and parallel clocks from the x6 clock line. The x6 clock line in transceiver bank 1 also drives the xN clock lines in transceiver bank 0. All bonded channels in transceiver bank 0 source both the serial and parallel clocks from the xN clock line.
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