Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

2.3.3. GXB 0 PPM Core Clock Assignment

The common clock should have a 0 PPM difference with respect to the read side of the TX FIFO (in the 10G PCS channel) or TX phase compensation FIFO (in the Standard PCS channel) of all the identical channels. A frequency difference causes the FIFO to under-run or overflow, depending on whether the common clock is slower or faster, respectively.

The 0 PPM common clock driver can be driven by one of the following sources:

  • tx_clkout in non-bonded channel configurations
  • tx_clkout[0] in bonded channel configurations
  • rx_clkout in non-bonded channel configurations
  • refclk when there is 0 PPM difference between refclk and tx_clkout
Table 21.  0 PPM Core Clock SettingsThe following table lists the 0 PPM core clock settings that you make in the Quartus II Assignment Editor.
Assignments9 Description
To tx_dataout/rx_datain pins of all channels whose tx/rx_coreclk ports are connected together and driven by the 0 PPM clock driver.
Assignment Name 0 PPM coreclk setting
Value ON
Note: For more information about QSF assignments and how 0 PPM is used with various transceiver PHYs, refer to the Altera Transceiver PHY IP Core User Guide.
9 You can find the full hierarchy name of the 0 PPM clock driver using the Node Finder feature in the Quartus II Assignment Editor.

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