Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.4.1. Transceiver Datapath Configuration

The transceiver datapaths for PCI Express are different depending on whether or not Gen3 is enabled.
Figure 101. PCIe Gen1 and Gen2 PIPE Datapath ConfigurationThis transceiver datapath configuration is for a configuration without Gen3 enabled.


Figure 102. PCIe Gen1, Gen2, and Gen3 Hard IP and PHY IP Core for PCI Express Datapath ConfigurationThis transceiver datapath configuration is for a configuration with Gen3 enabled.


Transceiver Channel Datapath

The following figure shows the Stratix V transmitter and receiver channel datapath for PCIe Gen1/Gen2 configurations when using PIPE configuration with Gen3 disabled. In this configuration, the transceiver connects to a PIPE 2.0 compliant interface.

Figure 103. Transceiver Channel Datapath for PCIe Gen1/Gen2 in PIPE Configuration with Gen3 Disabled


The following figure shows the Stratix V transmitter and receiver channel datapath for PCIe Gen1/Gen2/Gen3 configurations with a 32-bit PIPE 3.0-like interface and PCI Express Base Specification Version 3.0 is enabled.

Figure 104. Transceiver Channel Datapath for PCIe Gen1/Gen2/Gen3 Configurations


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