Stratix V Device Handbook: Volume 2: Transceivers

Download
ID 683779
Date 11/23/2021
Public
Document Table of Contents

4.3.3. Transceiver Clocking

Describes the transceiver clocking for the Interlaken protocol.
Figure 100. Clocking Resources Available in a Four-Lane Interlaken Configuration


A CMU PLL may provide a clock for up to five Interlaken lanes within a transceiver bank. If an ATX PLL is used, the PLL can clock up to six Interlaken lanes in a transceiver bank.

Note: To enable the ATX PLL, you must select ATX PLL for the PLL type parameter in the Interlaken PHY IP.

Did you find the information on this page useful?

Characters remaining:

Feedback Message