22.214.171.124.1. Non-Bonded Channel Configurations Using the x1 Clock Network 126.96.36.199.2. Non-Bonded Channel Configurations Using the xN Clock Network 188.8.131.52.3. Bonded Channel Configurations 184.108.40.206.4. Bonded Channel Configurations Using the xN Clock Network 220.127.116.11.5. Bonded Channel Configurations Using the PLL Feedback Compensation Path
3.2.1. User-Coded Reset Controller Signals 3.2.2. Resetting the Transmitter with the User-Coded Reset Controller During Device Power-Up 3.2.3. Resetting the Transmitter with the User-Coded Reset Controller During Device Operation 3.2.4. Resetting the Receiver with the User-Coded Reset Controller During Device Power-Up Configuration 3.2.5. Resetting the Receiver with the User-Coded Reset Controller During Device Operation
4.1. Protocols and Transceiver PHY IP Support 4.2. 10GBASE-R and 10GBASE-KR 4.3. Interlaken 4.4. PCI Express (PCIe)—Gen1, Gen2, and Gen3 4.5. XAUI 4.6. CPRI and OBSAI—Deterministic Latency Protocols 4.7. Transceiver Configurations 4.8. Native PHY IP Configuration 4.9. Stratix V GT Device Configurations 4.10. Document Revision History
4.2.1. 10GBASE-R and 10GBASE-KR Transceiver Datapath Configuration 4.2.2. 10GBASE-R and 10GBASE-KR Supported Features 4.2.3. 1000BASE-X and 1000BASE-KX Transceiver Datapath 4.2.4. 1000BASE-X and 1000BASE-KX Supported Features 4.2.5. Synchronization State Machine Parameters in 1000BASE-X and 1000BASE-KX Configurations 4.2.6. Transceiver Clocking in 10GBASE-R, 10GBASE-KR, 1000BASE-X, and 1000BASE-KX Configurations
4.4.1. Transceiver Datapath Configuration 4.4.2. Supported Features for PCIe Configurations 4.4.3. Supported Features for PCIe Gen3 4.4.4. Transceiver Clocking and Channel Placement Guidelines 4.4.5. Advanced Channel Placement Guidelines for PIPE Configurations 4.4.6. Transceiver Clocking for PCIe Gen3
6.1. Dynamic Reconfiguration Features 6.2. Offset Cancellation 6.3. PMA Analog Controls Reconfiguration 6.4. On-Chip Signal Quality Monitoring (Eye Viewer) 6.5. Decision Feedback Equalization 6.6. Adaptive Equalization 6.7. Dynamic Reconfiguration of Loopback Modes 6.8. Transceiver PLL Reconfiguration 6.9. Transceiver Channel Reconfiguration 6.10. Transceiver Interface Reconfiguration 6.11. Document Revision History
6.7. Dynamic Reconfiguration of Loopback Modes
You can enable the pre- and post-CDR reverse serial loopback modes by writing the appropriate bits of the Transceiver Reconfiguration Controller.
The following loopback paths are available:
- Serial loopback path— The output from the serializer is fed back to the CDR. While in this mode, the serializer also feeds the data to the TX output port. Enabling or disabling serial loopback mode is done through the PHY management interface.
- Post-CDR reverse serial loopback path— The RX captures the input data and feeds it into the CDR. The recovered data from the CDR output feeds into the TX driver and sends to the TX pins through the TX driver. For this path, the RX and CDR can be tested. For this path, the TX driver can be programmed to use either the main tap only or the main tap and the pre-emphasis first post-tap. Enabling or disabling the post-CDR reverse serial loopback modes is done through the PMA Analog Reconfiguration IP in the Transceiver Reconfiguration PHY IP.
- Pre-CDR reverse serial loopback path— The RX captures the input data and feeds it back to the TX driver through a buffer. With this path, you can perform a quick check for the quality of the RX and TX buffers. Enabling or disabling the pre-CDR reverse serial loopback mode.
Note: Serial loopback can be implemented with the transceiver PHY IP directly using the Avalon interface or a control port.
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