Stratix V Device Handbook: Volume 2: Transceivers

ID 683779
Date 2/15/2017
Public
Document Table of Contents

2.4. Document Revision History

The table below lists the revision history for this chapter.
Table 22.  Document Revision History
Date Version Changes
January 2016 2016.01.11 Added statement about powering up power pins to the "Dedicated refclk Pins" section.
September 2014 2014.09.30
  • Modifed Figure: Four Receiver Channels Configured in Bonded Duplex Configuration in " Bonded Channel Configurations" section to indicate that CMU PLL can support only four channels in a bonded configuration.
  • Modified Figure: Input Reference Clock Sources to Transmit PLLs and CDR and Figure: Fractional PLL Input Clock Sources. The reference clock network can be used as an input reference clock source and the dedicated reference clock pins feed the reference clock network.
  • Modified Figure: Transmitter Datapath Interface Clocking. The tx_clkout multiplexer is implemented in the FPGA fabric and is not present in the PCS.
  • Modified Figure: Receiver Datapath Interface Clocking. The rx_clkout multiplexer is implemented in the FPGA fabric and is not present in the PCS.
  • Updated the chapter to indicate that it is not recommended to use fractional PLL in fractional mode as a TX PLL or for PLL cascading.
  • Modified the definition of identical receiver channels in Selecting a Receiver Datapath Interface Clock section.
October 2013 2013.10.11
  • Updated "Dedicated refclk Pins" section.
May 2013 2013.05.06
  • Updated for Quartus II software version 13.0 feature support.
  • Added table "Electrical Specifications for the Input Reference Clock".
  • Added figure " Termination Scheme for a Reference Clock Signal When Configured as HCSL".
  • Updated table " Data Rates and Spans Supported Using Stratix V Clock Sources and Clock Networks".
  • Added information and figures for bonded and non-bonded channel configurations using the xN clock network.
  • Added link to the known document issues in the Knowledge Base.
December 2012 2012.12.17
  • Reorganized content and updated template.
  • Updated for the Quartus II software version 12.1.
  • Updated Figures 2-2, 2-3, 2-4, 2-5, 2-7, 2-8, 2-11, 2-21, and 2-26.
  • Added the “RX Pins Using the Reference Clock Network” section.
  • Updated table "Data Rates and Spans Supported Using Stratix V Clock Sources and Clock Networks."
  • Updated table "FPGA Fabric-Transceiver Interface Clocks" to address FB #60881.
  • Updated additional info in table "FPGA Fabric-Transceiver Interface Clocks" to address FB #65061.
  • Updated table "Configuration Specific Port Names for tx_clkout and rx_clkout."
June 2012 1.6
  • Updated for the Quartus II software version 12.0 and reordered paragraphs.
  • Added Clock Divider section previously located in Architecture chapter.
  • Added information about GXB 0 PPM core clock assignment.
  • Updated Figures 2-4, 2-7, 2-17, 2-21, 2-23, and 2-30.
February 2012 1.5
  • Updated document and figures for clarity.
  • Edited Figures 2-2, 2-3, and 2-4.
December 2011 1.4
  • Updated document and figures for clarity.
  • Changed path for serial and parallel clocks in channel 4 in Figure 2–14, Figure 2–20, and Figure 2–21.
November 2011 1.3
  • Added information about GT transceivers.
  • Added information about bonding channels across transceiver banks by using the PLL feedback compensation path.
  • x8 bonding using the xN clock lines is now available for PCIe Gen3.
  • Added information about the transceiver clocks used in the FPGA fabric.
  • Added information about fractional mode when using fractional PLLs.
  • Added information about using the FPGA fabric clocks as a reference clock to GX transceiver channels.
  • Added information about forwarding transceiver clocks to a fractional PLL so that the fractional PLL can synthesize a clock for the FPGA logic.
May 2011 1.2
  • Added information about fractional PLLs as they provide an input reference clock in “Input Reference Clocking.”
  • Chapter moved to Volume 3.
December 2010 1.1
  • Updated clock names.
  • Updated figures for more accurate depiction of transceiver clocking.
  • Added information about ATX PLLs.
July 2010 1.0 Initial release.

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