P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.1.4. Write Data Mover

The Write Data Mover has four user visible interfaces:
  • One Avalon® -MM Read Master with sideband signals to read data from the Avalon® domain.
  • Two Avalon® -ST Sinks to receive descriptors. One Sink acts as a queue for priority descriptors, and the other acts as a queue for normal descriptors.
  • One Avalon® -ST Source to report status

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