P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

2.1.3. Refclk

P-Tile has two reference clock inputs at the package level, refclk0 and refclk1. You must connect a 100 MHz reference clock source to these two inputs. Depending on the port mode, you can drive the two refclk inputs using either a single clock source or two independent clock sources.

In 1x16 and 4x4 modes, drive the refclk inputs with a single clock source (through a fanout buffer) as shown in the figure below.

Figure 4. Using a Single 100 MHz Clock Source in 1x16 and 4x4 Modes
In 2x8 mode, you can drive the refclk inputs with either a single 100 MHz clock source as shown above, or two independent 100 MHz sources (see the figure below) depending on your system architecture. For example, if your system has each x8 port connected to a separate CPU/Root Complex, it may be required to drive these refclk inputs using independent clock sources. In that case, it is strongly recommended that the refclk0 input for Port 0 (lanes 0 - 7) be always running because it feeds the reference clock for the P-Tile core PLL that controls the data transfers between the P-Tile and FPGA fabric via the EMIB. If this clock goes down, Port 0 link will go down and Port 1 will not be able to communicate with the FPGA fabric. Following are the guidelines for implementing two independent refclks in 2x8 mode:
  • If the link can handle two separate reference clocks, drive the refclk0 of P-Tile with the on-board free-running oscillator.
  • If the link needs to use a common reference clock, then PERST# needs to indicate the stability of this reference clock. If this reference clock goes down, the entire P-Tile must be reset.
Figure 5. Using Independent 100 MHz Clock Sources in 2x8 Mode

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