4.1. Overview 4.2. Clocks and Resets 4.3. Avalon® -MM Interface 4.4. Serial Data Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Hot Plug Interface (RP Only) 4.8. Power Management Interface 4.9. Configuration Output Interface 4.10. Hard IP Reconfiguration Interface 4.11. PHY Reconfiguration Interface
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h) A.2.2. Intel-Defined Vendor Specific Header (Offset 04h) A.2.3. Intel Marker (Offset 08h) A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.2.6. General Purpose Control and Status Register (Offset 0x30) A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.2.9. Correctable Internal Error Status Register (Offset 0x3C) A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
220.127.116.11.1. Bursting Avalon® -MM Master and Conduit in Non-Bursting Mode
In non-bursting mode, the Bursting Avalon® -MM Master module has the same interface as in bursting mode, except for some limitations in the size of transactions as described below:
- Burst count must be 1.
- The request size ranges from 1 to 16 dwords with the following limitations:
- The address and size combination must generate a TLP that fits in one 512-bit chunk of data. For example, if the address starts at dword 15 of a 512-bit transaction, only one dword of data transfer is allowed. If the address starts at dword 0, all data transfer sizes up to 16 dwords are possible. The same rule applies to read completions.
- Byte enables are supported for a transfer size of one dword. For larger transfer sizes, dword enables apply.
- If non-bursting mode is enabled, sending a TLP larger than 64 bytes targeting this interface causes the interface to misbehave. In this case, a reset is required to allow the interface to recover.
- One outstanding read at a time. Incoming RX read/write TLPs will be delayed while a downstream outstanding read exists.
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