P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Document Table of Contents

3.1. Top-Level Settings

Table 12.  Top-Level Settings
Parameter Value Default Value Description
Hard IP Mode

Gen4x16, Interface - 512-bit

Gen3x16, Interface - 512-bit

Gen4x8, Interface - 256-bit

Gen3x8, Interface - 256-bit

Gen4x4, Interface - 128-bit

Gen3x4, Interface - 128-bit

Gen4x16, Interface - 512-bit

Select the lane data rate and lane width.
Note: The lane data rate and lane width options shown here apply to the PCIe Hard IP interface to the Avalon® memory-mapped bridge. For the data rate and width on the interface between the Avalon® memory-mapped bridge and the application logic, refer to .
Note: Refer to the P-Tile IP for PCI Express* IP Core Release Notes for the matrix of configurations supported by the P-Tile Avalon® memory-mapped IP for PCI Express* .
Number of PCIe     Total number of cores. This parameter is set by the choice made for Hard IP Mode.
Port Mode

Root Port

Native Endpoint

Native Endpoint

Specifies the port type.
Enable PHY Reconfiguration True/False False Enable the PHY Reconfiguration Interface.
PLD Clock Frequency

400 MHz

350 MHz

250 MHz

125 MHz

350 MHz (for Gen4 mode)

250 MHz (for Gen3 modes)

Select the frequency of the Application clock. The options available vary depending on the setting of the Hard IP Mode parameter.

For Gen4 modes, the available clock frequencies are 400 MHz / 350 MHz / 250 MHz (for Intel® Agilex™ ) and 350 MHz / 200 MHz (for Intel® Stratix® 10 DX).

For Gen3 modes, the available clock frequencies are 250 MHz / 125 MHz (for Intel® Agilex™ ) and 250 MHz / 125 MHz (for Intel® Stratix® 10 DX).

For more details, refer to .

Enable SRIS Mode True/False False

Enable the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature.

When you enable this option, the Slot clock configuration option under the PCIeN SettingsPCIeN PCI Express/PCI CapabilitiesPCIeN Link tab will be automatically disabled.

P-Tile Sim Mode True/False False Enabling this parameter reduces the simulation time of Hot Reset tests by 5 ms.
Note: Do not enable this option if you need to run synthesis.
Enable RST of PCS & Controller True/False False

Enable the reset of PCS and Controller in User Mode for Endpoint and Bypass Upstream modes.

When this parameter is True, depending on the topology, new signals (p<n>_pld_clrpcs_n) are exported to the Avalon® Streaming interface.

When this parameter is False (default), the IP internally ties off these signals instead of exporting them.

Note: This parameter is required for the independent reset feature, which is only supported in the x8x8 Endpoint/Endpoint mode.
Note: Refer to Appendix E for more details regarding the independent resets feature and its usage.
Enable CVP (Intel VSEC) True/False False Enablement of CVP for a single tile only. Refer to https://www.intel.com/content/www/us/en/programmable/documentation/yiz1574399366423.html for more details on CVP.

The following figure shows how to enable Root Port mode:

Figure 13. Intel P-Tile Avalon® -MM Top-Level IP Parameter Editor for a Gen3x4 Hard IP in Root Port Mode

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