P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. Troubleshooting/Debugging 7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
2. IP Architecture and Functional Description x
2.1. Top-Level Architecture 2.2. Functional Description
2.1. Top-Level Architecture x
2.1.1. Avalon® -MM Bridge Architecture 2.1.2. Clock Domains 2.1.3. Refclk 2.1.4. Reset
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview 2.2.4. Avalon® -MM Bridge
2.2.4. Avalon® -MM Bridge x
2.2.4.1. Endpoint Mode with Data Movers 2.2.4.2. Endpoint Mode 2.2.4.3. Root Port Mode
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters 3.3. Avalon-MM Settings
3.2. Core Parameters x
3.2.1. Base Address Registers 3.2.2. PCI Express and PCI Capabilities Parameters 3.2.3. Device Identification Registers 3.2.4. Configuration, Debug and Extension Options
3.2.2. PCI Express and PCI Capabilities Parameters x
3.2.2.1. Device Capabilities 3.2.2.2. Link Capabilities 3.2.2.3. Legacy Interrupt Pin Register 3.2.2.4. MSI Capabilities 3.2.2.5. MSI-X Capabilities 3.2.2.6. Device Serial Number Capability 3.2.2.7. TLP Processing Hints (TPH)
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Avalon® -MM Interface 4.4. Serial Data Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Hot Plug Interface (RP Only) 4.8. Power Management Interface 4.9. Configuration Output Interface 4.10. Hard IP Reconfiguration Interface 4.11. PHY Reconfiguration Interface
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Interface Reset Signals
4.3. Avalon® -MM Interface x
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) 4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface)
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) x
4.3.1.1. Bursting Avalon® -MM Master and Conduit 4.3.1.2. Bursting Avalon® -MM Slave and Conduit 4.3.1.3. Read Data Mover 4.3.1.4. Write Data Mover 4.3.1.5. Descriptor Format for Data Movers 4.3.1.6. Avalon® -MM DMA Operations
4.3.1.1. Bursting Avalon® -MM Master and Conduit x
4.3.1.1.1. Bursting Avalon® -MM Master and Conduit in Non-Bursting Mode
4.3.1.2. Bursting Avalon® -MM Slave and Conduit x
4.3.1.2.1. Bursting Avalon® -MM Slave and Conduit in Non-Bursting Mode
4.3.1.3. Read Data Mover x
4.3.1.3.1. Read Data Mover Avalon® -MM Write Master and Conduit 4.3.1.3.2. Read Data Mover Avalon® -ST Descriptor Sinks 4.3.1.3.3. Read Data Mover Status Avalon® -ST Source
4.3.1.4. Write Data Mover x
4.3.1.4.1. Write Data Mover Avalon® -MM Read Master and Conduit 4.3.1.4.2. Write Data Mover Avalon® -ST Descriptor Sinks 4.3.1.4.3. Write Data Mover Status Avalon® -ST Source
4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface) x
4.3.2.1. High Performance Avalon® -MM Slave (HPTXS) Interface 4.3.2.2. High Performance Avalon® -MM Master (HPRXM) Interface 4.3.2.3. 32-Bit Control Register Access (CRA) Slave (Root Port only)
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.10. Hard IP Reconfiguration Interface x
4.10.1. Address Map for the User Avalon-MM Interface 4.10.2. Configuration Registers Access
4.10.2. Configuration Registers Access x
4.10.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.10.2.2. Using the Debug Register Interface Access
5. Advanced Features x
5.1. PCIe* Port Bifurcation and PHY Channel Mapping
6. Troubleshooting/Debugging x
6.1. Hardware 6.2. Debug Toolkit
6.1. Hardware x
6.1.1. Debugging Link Training Issues 6.1.2. Debugging Data Transfer and Performance Issues
6.1.1. Debugging Link Training Issues x
6.1.1.1. Generic Tools and Utilities 6.1.1.2. SignalTapII Logic Analyzer 6.1.1.3. Additional Debug Tools
6.1.2. Debugging Data Transfer and Performance Issues x
6.1.2.1. Advanced Error Reporting (AER) 6.1.2.2. Second-Level Debug Tools
6.2. Debug Toolkit x
6.2.1. Overview 6.2.2. Enabling the P-Tile Debug Toolkit 6.2.3. Launching the P-Tile Debug Toolkit 6.2.4. Using the P-Tile Debug Toolkit 6.2.5. Enabling the P-Tile Link Inspector 6.2.6. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Intel-Defined VSEC Capability Registers x
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h) A.2.2. Intel-Defined Vendor Specific Header (Offset 04h) A.2.3. Intel Marker (Offset 08h) A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.2.6. General Purpose Control and Status Register (Offset 0x30) A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.2.9. Correctable Internal Error Status Register (Offset 0x3C) A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers

3.1. Top-Level Settings

Table 12.  Top-Level Settings
Parameter Value Default Value Description
Hard IP Mode

Gen4x16, Interface - 512-bit

Gen3x16, Interface - 512-bit

Gen4x8, Interface - 256-bit

Gen3x8, Interface - 256-bit

Gen4x4, Interface - 128-bit

Gen3x4, Interface - 128-bit

Gen4x16, Interface - 512-bit

Select the lane data rate and lane width.
Note: The lane data rate and lane width options shown here apply to the PCIe Hard IP interface to the Avalon® memory-mapped bridge. For the data rate and width on the interface between the Avalon® memory-mapped bridge and the application logic, refer to Table 11.
Note: Refer to the P-Tile IP for PCI Express* IP Core Release Notes for the matrix of configurations supported by the P-Tile Avalon® memory-mapped IP for PCI Express* .
Number of PCIe     Total number of cores. This parameter is set by the choice made for Hard IP Mode.
Port Mode

Root Port

Native Endpoint

Native Endpoint

Specifies the port type.
Enable PHY Reconfiguration True/False False Enable the PHY Reconfiguration Interface.
Enable Ptile Debug Toolkit True/False False Enable the P-Tile Debug Toolkit for JTAG-based System Console debug access.
PLD Clock Frequency

400 MHz

350 MHz

250 MHz

125 MHz

350 MHz (for Gen4 mode)

250 MHz (for Gen3 modes)

Select the frequency of the Application clock. The options available vary depending on the setting of the Hard IP Mode parameter.

For Gen4 modes, the available clock frequencies are 400 MHz / 350 MHz / 250 MHz (for Intel® Agilex™ ) and 350 MHz / 200 MHz (for Intel® Stratix® 10 DX).

For Gen3 modes, the available clock frequencies are 250 MHz / 125 MHz (for Intel® Agilex™ ) and 250 MHz / 125 MHz (for Intel® Stratix® 10 DX).

For more details, refer to Table 11.

Clock Source

IOPLL

Clock Divider

IOPLL

Select Clock Divider to reclaim the IOPLL.

When the Clock Divider option is selected, the P-tile Avalon Streaming configuration does not instantiate any I/O bank IOPLL resource. This parameter is only available for Gen4 1x16 or Gen4 2x8 Hard IP modes when the PLD clock frequency is at 250 MHz or below.

Intel recommends using the IOPLL option. Only switch to Clock Divider when your design runs out of I/O Bank IOPLLs.
Note: Using Clock Divider may make timing closure more difficult.
Enable SRIS Mode True/False False

Enable the Separate Reference Clock with Independent Spread Spectrum Clocking (SRIS) feature.

When you enable this option, the Slot clock configuration option under the PCIeN Settings → PCIeN PCI Express/PCI Capabilities → PCIeN Link tab will be automatically disabled.

P-Tile Sim Mode True/False False Enabling this parameter reduces the simulation time of Hot Reset tests by 5 ms.
Note: Do not enable this option if you need to run synthesis.
Enable Independent Perst True/False False

Enable the reset of the Controller in User Mode for Endpoint and Bypass Upstream modes.

When this parameter is True, depending on the topology, new signals (p<n>_pld_cold_perst_n_i, p<n>_pld_warm_perst_n_i) are exported to the Avalon® Streaming interface.

When this parameter is False (default), the IP internally ties off these signals instead of exporting them.

Note: This parameter is required for the independent reset feature, which is only supported in Configuration Mode 1 (x8x8 Endpoint/Endpoint and x8x8 TLP Bypass UP/UP).
Note: Refer to Appendix E for more details regarding the independent resets feature and its usage.
Enable CVP (Intel VSEC) True/False False

When CvP is enabled and Configuration Mode 1 (x8x8 Endpoint / Endpoint and x8x8 TLP Bypass UP/UP) is selected, you must have Port 0 Device ID set to 0 and Port 1 Device ID set to other value. Otherwise, the CvP driver does not function properly.

Enablement of CvP for a single tile only. Refer to Intel Agilex Device Configuration via Protocol (CvP) Implementation User Guide for more details on CVP.

The following figure shows how to enable Root Port mode:

Figure 13. Intel P-Tile Avalon® -MM Top-Level IP Parameter Editor for a Gen3x4 Hard IP in Root Port Mode
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