P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

1.5. Performance and Resource Utilization

The following table shows the recommended FPGA fabric speed grades for all the configurations that the Avalon® -MM IP core supports.

Table 5.   Intel® Stratix® 10 DX / Intel® Agilex™ Recommended FPGA Fabric Speed Grades for All Avalon-MM Widths and FrequenciesThe recommended FPGA fabric speed grades are for production parts.

Lane Rate

Link Width

Application Interface Data Width

Application Clock Frequency (MHz)

Recommended FPGA Fabric Speed Grades

Gen4

x4 256-bit

200 MHz ( Intel® Stratix® 10 DX)

250 MHz ( Intel® Agilex™ )

-1, -2
x8 512-bit

200 MHz ( Intel® Stratix® 10 DX)

250 MHz ( Intel® Agilex™ )

-1, -2
x16 512-bit

350 MHz ( Intel® Stratix® 10 DX)

350 MHz / 400 MHz ( Intel® Agilex™ )

-1, -2

Gen3

x4 256-bit 125 MHz -1, -2

x8

512-bit 125 MHz -1, -2
x16 512-bit 250 MHz -1, -2

The Avalon® -MM variants include an Avalon® -MM DMA bridge implemented in soft logic. It operates as a front end to the hardened protocol stack. The resource utilization table below shows results for the Simple DMA dynamically generated design example.

The results are for the current version of the Intel® Quartus® Prime Pro Edition software.

Table 6.  Resource Utilization of the Avalon® -MM IP for PCI Express IP Core

Design Example Used

Link Configuration Device Family

Typical ALMs

M20K Memory Blocks2

Logic Registers

DMA Gen3 x16, EP Intel® Stratix® 10 DX 15956 120 42345
DMA Gen3 x16, EP Intel® Agilex™ 17116 120 42940
DMA Gen4 x16, EP Intel® Stratix® 10 DX 15967 120 42641
DMA Gen4 x16, EP Intel® Agilex™ 16963 120 45425
DMA Gen4 x8, EP Intel® Stratix® 10 DX 14533 97 42610
DMA Gen4 x8, EP Intel® Agilex™ 16275 97 41025
2 These results only include resources in the Avalon® -MM IP partition in the design example as the Table title indicates. They do not include resources for external blocks such as the on-chip memory, DMA controller, and other interconnect logic.

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