P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
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6.1.1.3. Additional Debug Tools

Use the Hard IP reconfiguration interface and PHY reconfiguration interface on the P-Tile Avalon® -MM IP for PCI Express to access additional registers (for example, receiver detection, lane reversal etc.).

Figure 37. Register Access for Debug

Using the Hard IP Reconfiguration Interface

Refer to the section Hard IP Reconfiguration Interface for details on this interface and the associated address map.

The following table lists the address offsets and bit settings for the PHY status registers. Use the Hard IP Reconfiguration Interface to access these read-only registers.

Table 61.  Hard IP Reconfiguration Interface Register Map for PHY Status
Offset Bit Position Register
0x0003E9 [0] RX polarity
[1] RX detection
[2] RX Valid
[3] RX Electrical Idle
[4] TX Electrical Idle
0x0003EC [7] Framing error
0x0003ED [7] Lane reversal
Follow the steps below to access registers in Table 61 using the Hard IP reconfiguration interface:
  1. Enable the Hard IP reconfiguration interface (User Avalon® -MM interface) using the IP Parameter Editor.
  2. Set the lane number for which you want to read the status by performing a read-modify-write to the address hip_reconfig_addr_i[20:0] with write data of lane number on hip_reconfig_writedata_i[7:0] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_write_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E8
    • hip_reconfig_writedata_i[3:0] = <Lane number>, where Lane number = 4’h0 for lane 0, 4’h1 for lane 1, 4’h2 for lane 2, …
  3. Read the status of the register you want by performing a read operation from the address hip_reconfig_addr_i[20:0] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_read_i = 1’b1
    • hip_reconfig_addr_i[20:0] = <offset>

      Offset = Refer to Table 61 for the offset mapping.

    • hip_reconfig_readdata_o[7:0] = Refer to Table 61 for the bit position mapping.
Example 1: To read the RX detection status of Lane0 using the registers
  1. Enable the Hard IP reconfiguration interface using the IP Parameter Editor.
  2. Perform read-modify-write to address 0x0003E8 to set the lane number to 0 using the Hard IP reconfiguration interface signals.
    • hip_reconfig_write_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E8
    • hip_reconfig_writedata_i[3:0] = 4'h0
  3. Read the status of the RX detection register by performing a read operation from the address 0x0003E9[1] using the Hard IP reconfiguration interface signals.
    • hip_reconfig_read_i = 1’b1
    • hip_reconfig_addr_i[20:0] = 0x0003E9
    • hip_reconfig_readdata_o[1] = 1'b1 (Far end receiver detected)

Using the PHY Reconfiguration Interface

Refer to the section PHY Reconfiguration Interface for details on how to use this interface.

Follow the steps below to access registers in Table 62 using the PHY reconfiguration interface.

  1. Enable the PHY reconfiguration interface using the IP Parameter Editor.
  2. Set the Quad and address offset from which you want to read the status by performing a read operation from the address xcvr_reconfig_addr_i[25:0] using the PHY reconfiguration interface signals.
    • xcvr_reconfig_read_i = 1’b1
    • xcvr_reconfig_addr_i[25:0] = {5-bit Quad mapping, 21-bit address offset}. Refer to Table 62 for the address offset and bit mapping.
    • xcvr_reconfig_readdata_o[7:0] = Refer to Table 62 for the address offset and bit mapping.
Table 62.  PHY Reconfiguration Interface Register Map for PHY Status
PHY Offset Bit Position Register
0x000006 [7]

PLLA state output status signal.

1'b1 indicates that PLLA is locked.

0x00000a [7]

PLLB state output status signal.

1'b1 indicates that PLLB is locked.

Example 2: To read the PLLA status using the registers
  1. Enable the PHY reconfiguration interface using the IP Parameter Editor.
  2. Perform a read from address 0x000006 to read the PLLA status output of Quad0 using the PHY reconfiguration interface signals.
    • xcvr_reconfig_read_i = 1'b1
    • xcvr_reconfig_addr_i[25:0] = 0x000006
    • xcvr_reconfig_readdata_o[7:0] = 8'h80
    • xcvr_reconfig_readdata_i = 1'b1 (PLLA state output high indicating PLL lock)

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