P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.1.4.3. Write Data Mover Status Avalon® -ST Source

Table 36.  Write Data Mover Status Avalon® -ST Source
Signal Name Direction Description Platform Designer Interface Name
wrdm_tx_data_o[31:0] O

[31:16]: reserved

[15]: error

[14:12] : application specific

[11:9] : reserved

[8] : priority bit

[7:0]: descriptor ID

wrdm_tx
wrdm_tx_valid_o O Valid status signal

This interface does not have a ready input. The application logic must always be ready to receive status information for any descriptor that it has sent to the Write Data Mover.

The ready latency does not matter because there is no ready input.

The Write Data Mover copies over the application specific bits in the wrdm_tx_data_o bus from the corresponding descriptor. A set priority bit indicates that the descriptor was from the priority descriptor sink.

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