P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.2.2. High Performance Avalon® -MM Master (HPRXM) Interface

The bursting Avalon® -MM master is always enabled in Root Port mode and is not associated with any BAR. Packets targeting addresses outside of the range of the base and limit registers are forwarded to the host via the HPRXM master. The bursting Avalon® -MM master has a 256-bit-wide data bus and supports up to 16-cycle bursts with dword granularity byte enable on the first and last cycles of a write burst and on single-cycle read bursts. Byte granularity access is supported for single-cycle one-dword or smaller transactions.

Table 41.  High Performance Avalon® -MM Master (HPRXM) Interface
Signal Name Direction Description Platform Designer Interface Name
rxm_write_o O Asserted by the core to request a write to an Avalon® -MM slave. hprxm_master
rxm_address_o[avmm_addr_width_hwtcl-1:0] O The address of the Avalon® -MM slave being accessed.
rxm_writedata_o[255:0] O This bus contains the RX data being written to the slave.
rxm_byteenable_o[31:0] O These bits specify the valid bytes for the write data.
rxm_burstcount_o[4:0] O The burst count, measured in qwords, of the RX write or read request. The maximum amount of data in a burst is 512 bytes.
rxm_waitrequest_i I When asserted by the external Avalon® -MM slave, this signal indicates that the slave is not ready for the next read or write request.
rxm_read_o O Asserted by the core to request a read.
rxm_readdata_i[255:0] I Read data returned from the Avalon® -MM slave in response to a read request. This data is sent to the IP core through the TX interface.
rxm_readdatavalid_i I Asserted by the system interconnect fabric to indicate that the read data is valid.

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