P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

2.1.2. Clock Domains

The P-Tile Avalon® -MM IP for PCI Express* has three primary clock domains:
  • PHY clock domain (i.e. core_clk domain): this clock is synchronous to the SerDes parallel clock.
  • EMIB/FPGA fabric interface clock domain (i.e. pld_clk domain): this clock is derived from the same reference clock (refclk0) as the one used by the SerDes. However, this clock is generated from a stand-alone core PLL.
  • Application clock domain (p<n>_app_clk): this clock is an output from the P-Tile IP. The frequency of this clock depends on the configuration that the IP is in. Refer to Table 11 below for more details. This is a per-port signal (i.e, n = 0,1,2,3).
Figure 3. Clock Domains

The PHY clock domain (i.e. core_clk domain) is a dynamic frequency domain. The PHY clock frequency is dependent on the current link speed.

Table 11.  PHY Clock and Application Clock Frequencies
Link Speed PHY Clock Frequency Application Clock Frequency
Gen1 125 MHz Gen1 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor.
Gen2 250 MHz Gen2 is supported only via link down-training and not natively. Hence, the application clock frequency depends on the configuration you choose in the IP Parameter Editor.
Gen3 500 MHz
Configuration EP/RP Data Width (bits) p<n>_app_clk Frequency (MHz)
Intel® Stratix® 10 DX Intel® Agilex™
Gen3 x4 RP 256 125 125
Gen3 x8 EP 512 125 125
Gen3 x16 EP 512 250 250
Gen4 1000 MHz
Configuration EP/RP Data Width (bits) p<n>_app_clk Frequency (MHz)
Intel® Stratix® 10 DX Intel® Agilex™
Gen4 x4 RP 256 200 250
Gen4 x8 EP 512 200 250
Gen4 x16 EP 512 350 400
Note: Refer to the P-Tile IP for PCI Express* IP Core Release Notes for the matrix of configurations supported by the P-Tile Avalon® memory mapped IP for PCI Express* .

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