P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

Download
ID 683268
Date 7/14/2021
Public
Document Table of Contents

3.2. Core Parameters

Depending on which Hard IP Mode you choose in the Top-Level Settings tab, you will see different tabs for setting the core parameters.

Figure 14. Intel P-Tile Avalon® -MM Top-Level IP Parameter Editor for a x8 Hard IP Mode If you choose a x8 mode (either Gen4 or Gen3), the PCIe0 Settings and PCIe1 Settings tabs will appear.

Did you find the information on this page useful?

Characters remaining:

Feedback Message