P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

3.2.4. Configuration, Debug and Extension Options

Table 21.  Configuration, Debug and Extension Options
Parameter Value Default Value Description
Gen 3 Requested equalization far-end TX preset vector 0 - 65535 0x00000004 Specifies the Gen 3 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.
Gen 4 Requested equalization far-end TX preset vector 0 - 65535 0x00000270 Specifies the Gen 4 requested phase 2/3 far-end TX preset vector. Choosing a value different from the default is not recommended for most designs.
Port 1 REFCLK Init Active True/False True

If this parameter is True (default), the refclk1 is stable after pin_perst and is free-running. This parameter must be set to True for Type A/B/C systems.

If this parameter is False, refclk1 is only available later in User Mode. This parameter must be set to False for Type D systems.

This parameter is only available in the PCIe1 Settings tab for a X8X8 topology.

Note: Refer to Appendix E for more details regarding the bifurcation feature and its usage.
Enable Debug Toolkit True/False False Enable the P-Tile Debug Toolkit for JTAG-based System Console debug access.
Enable HIP dynamic reconfiguration of PCIe* registers True/False False Enable the user Hard IP reconfiguration Avalon® -MM interface.
Figure 16. Configuration, Debug and Extension Parameters (with Debug Toolkit Enabled)

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