P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Document Table of Contents

4.2.2. Interface Reset Signals

Table 26.  Interface Reset Signals
Signal Name Direction Clock EP/RP Description
pin_perst_n Input Asynchronous EP/RP This is an active-low input to the PCIe* Hard IP, and implements the PERST# function defined by the PCIe* specification.
p<n>_reset_status_n Output Synchronous EP/RP This active-low signal is held low until pin_perst_n has been deasserted and the PCIe* Hard IP has come out of reset. This signal is synchronous to p<n>_app_clk. When port bifurcation is used, there is one such signal for each interface. The signals are differentiated by the prefixes p<n>.
p<n>_link_req_rst_n Output Synchronous EP/RP

This active-low signal is asserted by the PCIe Hard IP when it is about to go into reset.

The Avalon® -MM Bridge IP will reset all its PCIe-related registers and queues including anything related to tags. It will also stop sending packets to the PCIe Hard IP until the Bus Master Enable bit is set again. The Bridge will also ignore any packet received from the PCIe Hard IP.

p<n>_pld_warm_rst_rdy Input Synchronous EP/RP This active-high signal is asserted by the user logic in response to p<n>_link_req_rst_n when it has completed its pre-reset tasks.
Note: When not using this signal, set it to 1'b1.
ninit_done Input Asynchronous EP/RP

A "1" on this active-low signal indicates that the FPGA device is not yet fully configured. A "0" indicates the device has been configured and is in normal operating mode.

Intel recommends using the output of the Reset Release Intel Fpga IP to drive this ninit_done input. For more details on this IP, refer to the Application Note AN891 at Including the Reset Release Intel® FPGA IP in Your Design