P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

A.1.1. Register Access Definitions

This document uses the following abbreviations when describing register accesses.

Table 72.  Register Access Abbreviations
Abbreviation Meaning
RW Read and write access
RO Read only
WO Write only
RW1C Read write 1 to clear
RW1CS Read write 1 to clear sticky
RWS Read write sticky
Note: Sticky bits are not initialized or modified by hot reset.

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