7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
|Document Version||Intel® Quartus® Prime Version||IP Version||Changes|
|2021.07.14||21.1||4.0.0||Added a note to the Bursting Avalon-MM Master and Conduit and Bursting Avalon-MM Slave and Conduit sections stating that the Avalon memory-mapped addresses for those blocks must align to the widths of their data buses.|
|2021.03.29||21.1||4.0.0||Added a note to the Overview section stating that the P-Tile Avalon® Memory-mapped IP for PCI Express will not be available in future releases of Intel® Quartus® Prime.|
|2021.02.04||20.4||4.0.0||Fixed the direction of the p0_pld_link_req_rst_o signal in the block diagrams in the Avalon-MM Interface section.|
Added parameters to enable the independent resets for the x8x8 bifurcated mode to the Parameters chapter.
Added a note to the Interface Clock Signals section to clarify that coreclkout_hip is an internal clock only, and the Application layer must use the p<n>_app_clk clock instead.
Replaced all references to coreclkout_hip with p<n>_app_clk.
Removed the support for the Gen3 x4 256-bit and Gen4 x4 256-bit configurations from the IP Core and Design Example Support Levels section. This support may be available in a future release of Intel® Quartus® Prime.
Updated the app_clk frequencies in the Clock domains section.
Added Root Port settings to the Avalon® -MM Settings section.
Added support for the Gen3 x8 Endpoint and Gen4 x8 Endpoint modes to the Features chapter.
Updated the resource utilization numbers in the Resource Utilization chapter.
Added description for the Link Inspector in the Debug Toolkit chapter.
Added the lane reversal and polarity inversion support to the Features section.
Updated the bit ranges for the Next Capability Offset and Version fields in the Intel-Defined VSEC Capability Registers section.
Added clarification that VCS is the only simulator supported in the 20.1 release of Intel® Quartus® Prime. Also added that PIPE mode simulations are not supported in this release.
Changed the operation mode names from DMA Mode with Data Movers to Endpoint Mode with Data Movers, and from Bursting Slave Mode to Endpoint Mode.
Updated the document title to Intel FPGA P-Tile Avalon® memory mapped IP for PCI Express User Guide to meet new legal naming guidelines.
Updated the list of configurations supported in the Features section.
Replaced the Configuration Slave Interface with the Control Register Access Interface.
Added parameters in Intel® Quartus® Prime to control PASID and LTR.
Added MSI extended data support.
Added resource utilization numbers for the DMA design example in Intel® Stratix® 10 DX devices.
Added the step to choose Intel® Stratix® 10 DX devices to the Generating the Design Example section.
|2019.10.28||19.3||1.0.0||Removed a note containing a restriction on which normal descriptors cannot be interrupted by priority descriptors from the section Write Data Mover Avalon-ST Descriptor Sinks, because all normal descriptors being processed cannot be interrupted.|
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