P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.1.1. Bursting Avalon® -MM Master and Conduit

The Bursting Avalon® -MM Master module has one user-visible Avalon® -MM Master interface.

You enable this interface by turning On the Enable Bursting Avalon® -MM Master interface option in the Avalon® -MM Settings tab of the IP Parameter Editor.

Table 27.  Bursting Avalon® -MM Master and Conduit
Signal Name Direction Description Platform Designer Interface Name
bam_pfnum_o[1:0] O
Physical function number
  • PF0: bam_pfnum_o[1:0] = 2'b00
  • Others: bam_pfnum_o[1:0] = Reserved
bam_bar_o[2:0] O

This bus contains the BAR address for a particular TLP. This bus acts as an extension of the standard address bus.

000: Memory BAR 0

001: Memory BAR 1

010: Memory BAR 2

011: Memory BAR 3

100: Memory BAR 4

101: Memory BAR 5

110: Reserved

111: Expansion ROM BAR

bam_waitrequest_i I

When asserted, indicates that the Avalon® -MM slave is not ready to respond to a request.

waitrequestAllowance = 8

The master can still issue 8 transfers after bam_waitrequest_i is asserted.

bam_master
bam_address_o[BAM_ADDR_WIDTH-1:0] O

The width of the Bursting Master’s address bus is the maximum of the widths of all the enabled BARs.

For BARs narrower than the widest BAR, the address bus’ additional most significant (MSB) bits are driven to 0.

The Bursting Master's addresses must be aligned to the width of the data bus. For example, if the data width is 64B, the addresses must align to 64B.

bam_byteenable_o[63:0] O

Specify the valid bytes of bam_writedata_o[511:0]. Each bit corresponds to a byte in bam_writedata_o[511:0].

For single-cycle read bursts and for all write bursts, all contiguous sets of enabled bytes are supported.

For multi-cycle read bursts, all bits of bam_byteenable_o[63:0] are asserted, regardless of the First Byte Enable (BE) and Last BE fields of the corresponding TLP.

bam_read_o O When asserted, indicates the master is requesting a read transaction.
bam_readdata_i[511:0] I Read data bus
bam_readdatavalid_i I Asserted by the slave to indicate that the bam_readdata_i[511:0] bus contains valid data in response to a previous read request.
bam_write_o O When asserted, indicates the master is requesting a write transaction.
bam_writedata_o[511:0] O Data signals for write transfers.
bam_burstcount_o[3:0] O The master uses these signals to indicate the number of transfers in each burst.
bam_response_i[1:0] I

00 : OKAY - successful response for a transaction.

01 : RESERVED

10 : SLAVEERROR

11 : DECODEERROR

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