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1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers
4.1. Overview
4.2. Clocks and Resets
4.3. Avalon® -MM Interface
4.4. Serial Data Interface
4.5. Hard IP Status Interface
4.6. Interrupt Interface
4.7. Hot Plug Interface (RP Only)
4.8. Power Management Interface
4.9. Configuration Output Interface
4.10. Hard IP Reconfiguration Interface
4.11. PHY Reconfiguration Interface
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h)
A.2.2. Intel-Defined Vendor Specific Header (Offset 04h)
A.2.3. Intel Marker (Offset 08h)
A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18)
A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D)
A.2.6. General Purpose Control and Status Register (Offset 0x30)
A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34)
A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38)
A.2.9. Correctable Internal Error Status Register (Offset 0x3C)
A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
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3.2.2.3. Legacy Interrupt Pin Register
Parameter | Value | Default Value | Description |
---|---|---|---|
Enable Legacy Interrupts for PF0 | True/False | False | Enable Legacy Interrupts (INTx) for PF0 of PCIe0. |
Set Interrupt Pin for PF0 | NO INT INTA |
NO INT | When Legacy Interrupts are not enabled, the only option available is NO INT. When Legacy Interrupts are enabled, the only option available is INTA. |