P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

3.2.2.3. Legacy Interrupt Pin Register

Table 16.  Legacy Interrupts Parameters
Parameter Value Default Value Description
Enable Legacy Interrupts for PF0 True/False False Enable Legacy Interrupts (INTx) for PF0 of PCIe0.
Set Interrupt Pin for PF0

NO INT

INTA

NO INT

When Legacy Interrupts are not enabled, the only option available is NO INT.

When Legacy Interrupts are enabled, the only option available is INTA.

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