P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.8. Power Management Interface

Note: The Power Management interface is not available in the 20.4 release of Intel® Quartus® Prime. However, it may be available in a future release.

Software programs the device into a D-state by writing to the Power Management Control and Status register in the PCI Power Management Capability Structure. The power management output signals indicate the current power state. The IP core supports the two mandatory power states: D0 (full power) and D3 (preparation for a loss of power). It does not support the optional D1 and D2 low-power states.

The correspondence between the device power states (D states) and link power states (L states) is as follows:

Table 50.  Relationship Between Device and Link Power States
Device Power State Link Power State
D0 L0
D1 (not supported) L1
D2 (not supported) L1
D3 L1, L2/L3 Ready

P-Tile does not support ASPM.

Table 51.  Power Management Interface
Signal Name Direction Description Clock Domain EP/RP
pm_state_o[2:0] O Indicates the current power state. p<n>_app_clk EP/RP

x16/x8: pm_dstate_o[31:0]

x4: pm_dstate_o[3:0]

O Power management D-state for each function.
  • 0001b : D0
  • 0010b : D1
  • 0100b : D2
  • 1000b : D3
  • 0000b : uninitialized or invalid
Async EP/RP

x16/x8: apps_pm_xmt_pme_i[7:0]

x4: NA

I The application logic asserts this signal for one cycle to wake up the Power Management Capability (PMC) state machine from a D1, D2, or D3 power state. Upon wake-up, the IP core sends a PM_PME message. p<n>_app_clk EP

x16/x8: app_ready_entr_l23_i

x4: NA

I The application logic asserts this signal to indicate that it is ready to enter the L2/L3 Ready state. The app_ready_entr_l23_i signal is provided for applications that must control the L2/L3 Ready entry (in case certain tasks must be performed before going into L2/L3 Ready). The core delays sending PM_Enter_L23 (in response to PM_Turn_Off) until this signal becomes active. This is a level-sensitive signal. p<n>_app_clk EP

x16: app_req_retry_en_i[7:0]

x8: app_req_retry_en_i

x4: NA

I

When these signals are asserted, the P-Tile Avalon® -MM IP will respond to Configuration TLPs with a Configuration Retry Status (CRS) if it is not ready to respond with non-CRS status since the last reset.

For x4 ports, this signal is not used and needs to be driven to zero.

Async EP

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