P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.3.1.2.1. Bursting Avalon® -MM Slave and Conduit in Non-Bursting Mode

The Bursting Avalon® -MM Slave module supports bursting mode while operating in Root Port mode.

This module can also operate in non-bursting mode. In this mode, the module interface is the same as in bursting mode except that it has limitations in the size of transactions as described below:
  • Burst count must be 1.
  • The request size ranges from 1 to 16 dwords with the following limitations:
    • The address and size combination must generate a TLP that fits in one 512B chunk of data. For example, if the address starts at dword 15 of a 512B transaction, only one dword of data transfer is allowed. If the address starts at dword 0, all data transfer sizes up to 16 dwords are possible. The same rule applies to read completions.
    • Byte enables are supported for a transfer size of one dword. For larger transfer sizes, dword enables apply.
  • One outstanding read at a time (back-pressures the Avalon® -MM Master while the outstanding read exists).

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