P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

4.1. Overview

The P-Tile Avalon-MM IP for PCIe includes many interface types to implement different functions.These include:
  • High-performance bursting master (BAM) and slave (BAS) Avalon® -MM interfaces to translate between PCIe TLPs and Avalon® -MM memory-mapped reads and writes
  • Read and Write Data Movers to transfer large blocks of data
  • Standard PCIe serial interface to transfer data over the PCIe link
  • System interfaces for interrupts, clocking, reset
  • Optional reconfiguration interface to dynamically change the value of Configuration Space registers at run-time
  • Optional status interface for debug
Unless otherwise noted, all interfaces to the Application Layer are synchronous to the rising edge of app_clk. You enable the interfaces using the component IP Parameter Editor.

Read Data Mover (RDDM) interface: This interface transfers DMA data from the PCIe system memory to the memory in Avalon® -MM address space.

Write Data Mover (WRDM) interface: This interface transfers DMA data from the memory in Avalon® -MM address space to the PCIe system memory.

Bursting Master (BAM) interface: This interface provides host access to the registers and memory in Avalon® -MM address space. The Busting Master module converts PCIe Memory Reads and Writes to Avalon® -MM Reads and Writes.

Bursting Slave (BAS) interface: This interface allows the user application in the FPGA to access the PCIe system memory. The Bursting Slave module converts Avalon® -MM Reads and Writes to PCIe Memory Reads and Writes.

Control Register Access (CRA) interface: This optional, 32-bit Avalon-MM Slave interface provides access to the Control and Status registers. You must enable this interface when you enable address mapping for any of the Avalon-MM slaves or if interrupts are implemented. The address bus width of this interface is fixed at 15 bits. The prefix for this interface is cra*.

The modular design of the P-Tile Avalon® -MM IP for PCIe lets you enable just the interfaces required for your application.

Table 23.   Avalon® -MM Interface Summary
Avalon® -MM Type Data Bus Width Max Burst Size Byte Enable Granularity Max Outstanding Read Request
Bursting Slave 512 bits

Bursting Mode: 8 cycles

Non-Bursting Mode: 1 cycle

dword/byte

Bursting Mode: 64

Non-Bursting Mode: 1

Bursting Master 512 bits

Bursting Mode: 8 cycles

Non-Bursting Mode: 1 cycle

dword/byte

Bursting Mode: 32

Non-Bursting Mode: 1

Read Data Mover Write Master 512 bits 8 cycles dword N/A
Write Data Mover Read Master 512 bits 8 cycles dword 32
Control Register Access 32 bits 1 cycle byte 1
Note: The number of read requests issued by the Write Data Mover's Avalon® -MM Read Master is controlled by the assertion of waitrequest by the connected slave(s). The Read Master can handle 128 outstanding cycles of data. You cannot set this parameter in Platform Designer. The slave needs to correctly back-pressure the master once it cannot handle the incoming requests.
Note: The 512-bit Bursting Slave interface does not support transactions where all byte enables are set to 0.
Note: All transfers of four bytes or more are done in multiples of dwords.

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