18.104.22.168. Endpoint Mode with Data Movers
- Read Data Mover (RDDM)
- Write Data Mover (WRDM)
- Bursting Master (BAM) in Non-Bursting Mode
The following figure shows how the DMA example design that you can generate using the Intel® Quartus® Prime software interfaces with the P-Tile Avalon® -MM IP to perform DMA operations. If you are not using the provided DMA example design, you need to implement your custom DMA Controller and BAR Interpreter in your application logic.
In this DMA example design, the BAM is used in non-bursting mode by the host to program the Control and Status registers of the DMA controller in the user Avalon® -MM space. The DMA controller, after being programmed, sends descriptor-fetching instructions to the host via the RDDM. After the fetched descriptors are processed by the WRDM and RDDM, status and/or MSI-X messages are sent to the host via the WRDM in “Immediate” mode. In this mode, the data payload is embedded in bits [31:0] or [63:0] of the fetched descriptors that the WRDM receives (depending on whether a one- or two-dword immediate transfer is needed respectively). For more details on immediate transfers, refer to Write Data Mover Avalon -ST Descriptor Sinks.
The RDDM uses PCIe memory read TLPs and Avalon® -MM write transactions (which can be bursting transactions) to move large amounts of data from the host memory in PCIe space to the local FPGA memory in Avalon® -MM space. On the other hand, the WRDM uses PCIe memory write TLPs and Avalon® -MM read transactions to move large amounts of data from the FPGA memory in Avalon® -MM space to the host memory in PCIe space. The Data Movers' transfers are controlled by descriptors that are provided to the Data Movers through one of their Avalon® -ST sink interfaces. The Data Movers report the transfers’ status through their Avalon® -ST source interfaces.
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