P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

6.2.1. Overview

The P-Tile Debug Toolkit is a System Console-based tool for P-Tile that provides real-time control, monitoring and debugging of the PCIe links at the Physical, Data Link and Transaction layers.

The P-Tile Debug Toolkit allows you to:

  • View protocol and link status of the PCIe links per port.
  • View PLL and per-channel status of the PCIe links per port.
  • Control the channel analog settings.
  • View the receiver eye and measure the eye height and width.
  • Indicate the presence of a re-timer connected between the link partners.

The following figure provides an overview of the P-Tile Debug Toolkit in the P-Tile Avalon® -MM IP for PCI Express.

Figure 38. Overview of the P-Tile Debug Toolkit

When you enable the P-Tile Debug Toolkit, the intel_pcie_ptile_avmm module of the generated IP includes the Debug Toolkit modules and related logic as shown in the figure above.

Drive the Debug Toolkit from a System Console. The System Console connects to the Debug Toolkit via an Native PHY Debug Master Endpoint (NPDME). Make this connection via an Intel FPGA Download Cable.

This PHY reconfiguration interface clock (xcvr_reconfig_clk) is used to clock the following interfaces:
  • The NPDME module
  • PHY reconfiguration interface (xcvr_reconfig)
  • Hard IP reconfiguration interface (hip_reconfig)

Provide a clock source (50 MHz - 125 MHz, 100 MHz recommended clock frequency) to drive the xcvr_reconfig_clk clock. Use the output of the Reset Release Intel FPGA IP to drive the ninit_done, which provides the reset signal to the NPDME module.

Note: When using the port bifurcation feature, always connect the xcvr_reconfig_clk of Port0 to a clock source. This signal is used to provide the clock to the Debug Toolkit.
Note: When you enable the P-Tile Debug Toolkit, the Hard IP reconfiguration interface is enabled by default.
When you run a dynamically-generated design example on the Intel Development Kit, make sure that clock and reset signals are connected to their respective sources and appropriate pin assignments are made. Here are some sample .qsf assignments for the Debug Toolkit for Intel® Stratix® 10 DX devices:
  • set_location_assignment PIN_A31 -to p0_hip_reconfig_clk_clk
  • set_location_assignment PIN_C23 -to xcvr_reconfig_clk_clk

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