P-tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683268
Date 7/14/2021
Public
Document Table of Contents

A.1.2. PCIe Configuration Header Registers

The Corresponding Section in PCIe Specification column in the tables in the Configuration Space Registers section lists the appropriate sections of the PCI Express Base Specification that describe these registers.

Figure 52. PCIe Type 0 Configuration Space Registers - Byte Address Offsets and Layout
Figure 53. PCIe Type 1 Configuration Space Registers - Byte Address Offsets and Layout

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