P-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

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ID 683268
Date 7/14/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express 2. IP Architecture and Functional Description 3. Parameters 4. Interfaces 5. Advanced Features 6. Troubleshooting/Debugging 7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide A. Configuration Space Registers
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express x
1.1. Overview 1.2. Features 1.3. Release Information 1.4. Device Family Support 1.5. Performance and Resource Utilization 1.6. IP Core and Design Example Support Levels
2. IP Architecture and Functional Description x
2.1. Top-Level Architecture 2.2. Functional Description
2.1. Top-Level Architecture x
2.1.1. Avalon® -MM Bridge Architecture 2.1.2. Clock Domains 2.1.3. Refclk 2.1.4. Reset
2.2. Functional Description x
2.2.1. PMA/PCS 2.2.2. Data Link Layer Overview 2.2.3. Transaction Layer Overview 2.2.4. Avalon® -MM Bridge
2.2.4. Avalon® -MM Bridge x
2.2.4.1. Endpoint Mode with Data Movers 2.2.4.2. Endpoint Mode 2.2.4.3. Root Port Mode
3. Parameters x
3.1. Top-Level Settings 3.2. Core Parameters 3.3. Avalon-MM Settings
3.2. Core Parameters x
3.2.1. Base Address Registers 3.2.2. PCI Express and PCI Capabilities Parameters 3.2.3. Device Identification Registers 3.2.4. Configuration, Debug and Extension Options
3.2.2. PCI Express and PCI Capabilities Parameters x
3.2.2.1. Device Capabilities 3.2.2.2. Link Capabilities 3.2.2.3. Legacy Interrupt Pin Register 3.2.2.4. MSI Capabilities 3.2.2.5. MSI-X Capabilities 3.2.2.6. Device Serial Number Capability 3.2.2.7. TLP Processing Hints (TPH)
4. Interfaces x
4.1. Overview 4.2. Clocks and Resets 4.3. Avalon® -MM Interface 4.4. Serial Data Interface 4.5. Hard IP Status Interface 4.6. Interrupt Interface 4.7. Hot Plug Interface (RP Only) 4.8. Power Management Interface 4.9. Configuration Output Interface 4.10. Hard IP Reconfiguration Interface 4.11. PHY Reconfiguration Interface
4.2. Clocks and Resets x
4.2.1. Interface Clock Signals 4.2.2. Interface Reset Signals
4.3. Avalon® -MM Interface x
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) 4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface)
4.3.1. Endpoint Mode Interface (512-bit Avalon® -MM Interface) x
4.3.1.1. Bursting Avalon® -MM Master and Conduit 4.3.1.2. Bursting Avalon® -MM Slave and Conduit 4.3.1.3. Read Data Mover 4.3.1.4. Write Data Mover 4.3.1.5. Descriptor Format for Data Movers 4.3.1.6. Avalon® -MM DMA Operations
4.3.1.1. Bursting Avalon® -MM Master and Conduit x
4.3.1.1.1. Bursting Avalon® -MM Master and Conduit in Non-Bursting Mode
4.3.1.2. Bursting Avalon® -MM Slave and Conduit x
4.3.1.2.1. Bursting Avalon® -MM Slave and Conduit in Non-Bursting Mode
4.3.1.3. Read Data Mover x
4.3.1.3.1. Read Data Mover Avalon® -MM Write Master and Conduit 4.3.1.3.2. Read Data Mover Avalon® -ST Descriptor Sinks 4.3.1.3.3. Read Data Mover Status Avalon® -ST Source
4.3.1.4. Write Data Mover x
4.3.1.4.1. Write Data Mover Avalon® -MM Read Master and Conduit 4.3.1.4.2. Write Data Mover Avalon® -ST Descriptor Sinks 4.3.1.4.3. Write Data Mover Status Avalon® -ST Source
4.3.2. Root Port Mode Interface (256-bit Avalon® -MM Interface) x
4.3.2.1. High Performance Avalon® -MM Slave (HPTXS) Interface 4.3.2.2. High Performance Avalon® -MM Master (HPRXM) Interface 4.3.2.3. 32-Bit Control Register Access (CRA) Slave (Root Port only)
4.6. Interrupt Interface x
4.6.1. Legacy Interrupts 4.6.2. MSI 4.6.3. MSI-X
4.6.3. MSI-X x
4.6.3.1. Implementing MSI-X Interrupts
4.10. Hard IP Reconfiguration Interface x
4.10.1. Address Map for the User Avalon-MM Interface 4.10.2. Configuration Registers Access
4.10.2. Configuration Registers Access x
4.10.2.1. Using Direct User Avalon-MM Interface (Byte Access) 4.10.2.2. Using the Debug Register Interface Access
5. Advanced Features x
5.1. PCIe* Port Bifurcation and PHY Channel Mapping
6. Troubleshooting/Debugging x
6.1. Hardware 6.2. Debug Toolkit
6.1. Hardware x
6.1.1. Debugging Link Training Issues 6.1.2. Debugging Data Transfer and Performance Issues
6.1.1. Debugging Link Training Issues x
6.1.1.1. Generic Tools and Utilities 6.1.1.2. SignalTapII Logic Analyzer 6.1.1.3. Additional Debug Tools
6.1.2. Debugging Data Transfer and Performance Issues x
6.1.2.1. Advanced Error Reporting (AER) 6.1.2.2. Second-Level Debug Tools
6.2. Debug Toolkit x
6.2.1. Overview 6.2.2. Enabling the P-Tile Debug Toolkit 6.2.3. Launching the P-Tile Debug Toolkit 6.2.4. Using the P-Tile Debug Toolkit 6.2.5. Enabling the P-Tile Link Inspector 6.2.6. Using the P-Tile Link Inspector
A. Configuration Space Registers x
A.1. Configuration Space Registers A.2. Intel-Defined VSEC Capability Registers
A.1. Configuration Space Registers x
A.1.1. Register Access Definitions A.1.2. PCIe Configuration Header Registers A.1.3. PCI Express Capability Structures A.1.4. Physical Layer 16.0 GT/s Extended Capability Structure A.1.5. MSI-X Registers
A.2. Intel-Defined VSEC Capability Registers x
A.2.1. Intel-Defined VSEC Capability Header (Offset 00h) A.2.2. Intel-Defined Vendor Specific Header (Offset 04h) A.2.3. Intel Marker (Offset 08h) A.2.4. JTAG Silicon ID (Offset 0x0C - 0x18) A.2.5. User Configurable Device and Board ID (Offset 0x1C - 0x1D) A.2.6. General Purpose Control and Status Register (Offset 0x30) A.2.7. Uncorrectable Internal Error Status Register (Offset 0x34) A.2.8. Uncorrectable Internal Error Mask Register (Offset 0x38) A.2.9. Correctable Internal Error Status Register (Offset 0x3C) A.2.10. Correctable Internal Error Mask Register (Offset 0x40)
1. About the P-tile Avalon® Intel® FPGA IPs for PCI Express
2. IP Architecture and Functional Description
3. Parameters
4. Interfaces
5. Advanced Features
6. Troubleshooting/Debugging
7. Document Revision History for the P-tile Avalon® Memory-mapped Intel FPGA IP for PCI Express User Guide
A. Configuration Space Registers

A.1. Configuration Space Registers

In addition to accessing the Endpoint's configuration space registers by sending Configuration Read/Write TLPs via the Avalon® -ST interface, the application logic can also gain read access to these registers via the Configuration Output Interface (tl_cfg*). Furthermore, the Hard IP Reconfiguration Interface (a User Avalon® -MM interface) also provides read/write access to these registers.

For signal timings on the User Avalon® -MM interface, refer to the Avalon® Interface Specifications document.

The table PCIe Configuration Space Registers describes the registers for each PF. To calculate the address for a particular register in a particular PF, add the offset for that PF from the table Configuration Space Offsets to the byte address for that register as given in the table PCIe Configuration Space Registers.

Table 71.  Configuration Space Offsets
Registers User Avalon® -MM Offsets
Physical function 0 0x0000
Physical function 1 0x1000
Physical function 2 0x2000
Physical function 3 0x3000
Physical function 4 0x4000
Physical function 5 0x5000
Physical function 6 0x6000
Physical function 7 0x7000
User Avalon-MM Control Register 0x104068
Debug (DBI) Register 0x104200, 0x104204
Note: In 1x8 EP mode, only the x16 (Port 0) core is active.
Table 72.  PCIe Configuration Space Registers for x16/x8/x4 Controllers
Byte Address Hard IP Configuration Space Register Corresponding Section in PCIe Specification

x16 (Port 0) = 0x000 : 0x03C

x8 (Port 1) = 0x000 : 0x03C

x4 (Ports 2,3) = 0x000 : 0x03C

 PCI Header Type 0/1 Configuration Registers Type 0/1 Configuration Space Header

x16 (Port 0) = 0x040 : 0x044

x8 (Port 1) = 0x040 : 0x044

x4 (Ports 2,3) = 0x040 : 0x044

 Power Management PCI Power Management Capability Structure

x16 (Port 0) = 0x050 : 0x064

x8 (Port 1) = 0x050 : 0x064

x4 (Ports 2,3) = 0x050 : 0x05c

 MSI Capability

MSI Capability Structure, see also PCI Local Bus Specification

x16 (Port 0) = 0x070 : 0x0A8

x8 (Port 1) = 0x070 : 0x0A8

x4 (Ports 2,3) = 0x070 : 0x0A8

 PCI Express Capability PCI Express Capability Structure

x16 (Port 0) = 0x0B0 : 0x0B9

x8 (Port 1) = 0x0B0 : 0x0B9

x4 (Ports 2,3) = 0x0B0 : 0x0B9

 MSI-X Capability MSI-X Capability Structure, see also PCI Local Bus Specification

x16 (Port 0) = 0x0BC : 0x0FC

x8 (Port 1) = 0x0BC : 0x0FC

x4 (Ports 2,3) = 0x0BC : 0x0FC

 Reserved N/A

x16 (Port 0) = 0x100 : 0x144

x8 (Port 1) = 0x100 : 0x144

x4 (Ports 2,3) = 0x100 : 0x144

 Advanced Error Reporting (AER) Advanced Error Reporting Capability Structure

x16 (Port 0) = 0x148 : 0x164

x8 (Port 1) = 0x148 : 0x164

x4 (Ports 2,3) = 0x148 : 0x164

 Virtual Channel Capability Virtual Channel Capability Structure

x16 (Port 0) = 0x178 : 0x17C

x8 (Port 1) = 0x178 : 0x17C

x4 (Ports 2,3) = N/A

 Alternative Routing-ID Implementation (ARI) ARI Capability Structure

x16 (Port 0) = 0x188 : 0x1B4

x8 (Port 1) = 0x188 : 0x1A4

x4 (Ports 2,3) = 0x188 : 0x1A4

Secondary PCI Express Extended Capability Header

 PCI Express Extended Capability

x16 (Port 0) = 0x1B8 : 0x1E4

x8 (Port 1) = 0x1A8 : 0x1CC

x4 (Ports 2,3) = 0x1A8 : 0x1C8

 Physical Layer 16.0 GT/s Extended Capability Physical Layer 16.0 GT/s Extended Capability Structure

x16 (Port 0) = 0x1E8 : 0x22C

x8 (Port 1) = 0x1D0 : 0x1F4

x4 (Ports 2,3) = 0x1CC : 0x1E0

 Margining Extended Capability Margining Extended Capability Structure

x16 (Port 0) = 0x230 : 0x26C

x8 (Port 1) = 0x1F8 : 0x234

x4 (Ports 2,3) = N/A

 SR-IOV Capability SR-IOV Capability Structure

x16 (Port 0) = 0x270 : 0x2F8

x8 (Port 1) = 0x238 : 0x2C0

x4 (Ports 2,3) = 0x1E4 : 0x26C

 TLP Processing Hints (TPH) Capability TLP Processing Hints (TPH) Capability Structure

x16 (Port 0) = 0x2FC : 0x300

x8 (Port 1) = 0x2C4 : 0x2C8

x4 (Ports 2,3) = N/A

 Address Translation Services (ATS) Capability Address Translation Services Extended Capability (ATS) in Single Root I/O Virtualization and Sharing Specification

x16 (Port 0) = 0x30C : 0x314

x8 (Port 1) = 0x2D4 : 0x2DC

x4 (Ports 2,3) = 0x280 : 0x288

 Access Control Services (ACS) Capability Access Control Services (ACS) Capability

x16 (Port 0) = 0x318 : 0x324

x8 (Port 1) = 0x2E0 : 0x2EC

x4 (Ports 2,3) = N/A

 Page Request Services (PRS) Capability Page Request Services (PRS) Capability

x16 (Port 0) = 0x328 : 0x32C

x8 (Port 1) = 0x2F0 : 0x2F4

x4 (Ports 2,3) = N/A

 Latency Tolerance Reporting (LTR) Capability Latency Tolerance Reporting (LTR) Capability

x16 (Port 0) = 0x330 : 0x334

x8 (Port 1) = 0x2F8 : 0x2FC

x4 (Ports 2,3) = N/A

 Process Address Space (PASID) Capability Process Address Space (PASID) Capability Structure

x16 (Port 0) = 0x338 : 0x434

x8 (Port 1) = 0x300 : 0x3FC

x4 (Ports 2,3) = 0x2AC : 0x3A8

 RAS D.E.S. Capability (VSEC)  

x16 (Port 0) = 0x470 : 0x478

x8 (Port 1) = 0x438 : 0x440

x4 (Ports 2,3) = 0x3E4 : 0x3EC

 Data Link Feature Extended Capability  

x16 (Port 0) = 0xD00 : 0xD58

x8 (Port 1) = 0xD00 : 0xD58

x4 (Ports 2,3) = 0xD00 : 0xD58

 Intel-defined VSEC  

Section Content
Register Access Definitions
PCIe Configuration Header Registers
PCI Express Capability Structures
Physical Layer 16.0 GT/s Extended Capability Structure
MSI-X Registers

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